From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50349) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPrIM-0003wY-Vj for qemu-devel@nongnu.org; Tue, 18 Mar 2014 06:31:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPrIF-0007jz-N1 for qemu-devel@nongnu.org; Tue, 18 Mar 2014 06:30:54 -0400 Received: from david.siemens.de ([192.35.17.14]:40574) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPrIF-0007jt-DE for qemu-devel@nongnu.org; Tue, 18 Mar 2014 06:30:47 -0400 Message-ID: <53282052.1020909@siemens.com> Date: Tue, 18 Mar 2014 11:30:42 +0100 From: Jan Kiszka MIME-Version: 1.0 References: <20140317215455.2f14b61f@redhat.com> <5327F398.7040509@siemens.com> <5327F771.7040205@redhat.com> In-Reply-To: <5327F771.7040205@redhat.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH for-2.0?] target-i386: fix gdb debugging with large memory guests List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , Luiz Capitulino , qemu-devel Cc: peter.maydell@linaro.org, afaerber@suse.de On 2014-03-18 08:36, Paolo Bonzini wrote: > Il 18/03/2014 08:19, Jan Kiszka ha scritto: >> On 2014-03-18 02:54, Luiz Capitulino wrote: >>> If you start a Linux guest with more than 4GB of memory and try to >>> look at a >>> memory address, you will get an error from gdb: >>> >>> (gdb) p node_data[0]->node_id >>> Cannot access memory at address 0xffff88013fffd3a0 >>> (gdb) >> >> I suppose this is x86-64, not 32-bit with PTE, right? >> >>> >>> I debugged this down to x86_cpu_get_phys_page_debug(), it doesn't >>> handle the >>> case where the PDPTE has the PS bit set (although I didn't check >>> where Linux >>> sets that bit). This commit adds the PS bit handling, which fixes the >>> problem >>> for me. >>> >>> Signed-off-by: Luiz capitulino >>> --- >>> >>> Two observations: >>> >>> 1. This bug has always existed, so it's not a regression, so I'm not >>> sure >>> it's worth it to fix for 2.0 > > Sure, why not? > >>> 2. I'm not familiar with every detail of x86_cpu_get_phys_page_debug(), >>> so I'm not completely sure this is the right thing to do >>> >>> target-i386/helper.c | 8 ++++++++ >>> 1 file changed, 8 insertions(+) >>> >>> diff --git a/target-i386/helper.c b/target-i386/helper.c >>> index 4f447b8..9b7803f 100644 >>> --- a/target-i386/helper.c >>> +++ b/target-i386/helper.c >>> @@ -951,6 +951,13 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, >>> vaddr addr) >>> return -1; >>> } >>> >>> + if (pdpe & PG_PSE_MASK) { >>> + page_size = 1024 * 1024 * 1024; >>> + pte = pdpe & ~( (page_size - 1) & ~0xfff); >>> + pte &= ~(PG_NX_MASK | PG_HI_USER_MASK); >>> + goto out; >>> + } >> >> Does this also apply if we are not in long mode? > > No, it doesn't. The only valid bits in a PAE PDPTE are P, PWT and PCD. > Bit 7 (PS) is reserved. Right, this belongs in the "if (env->hflags & HF_LMA_MASK)" block. And the subject or description should mention that x86_cpu_get_phys_page_debug was lacking support for 1G hugepages. Jan -- Siemens AG, Corporate Technology, CT RTC ITP SES-DE Corporate Competence Center Embedded Linux