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Subject: Re: [Qemu-devel] target-i386: guest variable shift by 0 provokes
	shift by -1
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>

On 03/18/2014 08:01 AM, Peter Maydell wrote:
> Unless all our host architectures have undefined-result
> behaviour for variable shifts by out of range values
> then we can't make the TCG op semantics do that.
> (They probably can; the only counterexample I know
> of is the 8086, where the variable-shift cycle count
> was proportional to the value of the shift, so feeding
> it -1 would effectively cause it to hang.)

ARM is our only host architecture that does not mask the input to the width of
the operand.  That one, of course, masks with 255 and produces zero for shifts
larger than the width of the operand.

There are several host architectures for which we do not have backends that
e.g. always mask with 63, even for the 32-bit shifts.


r~