From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42456) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQ2Qn-00061C-Kd for qemu-devel@nongnu.org; Tue, 18 Mar 2014 18:24:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WQ2Qh-0007o0-Pr for qemu-devel@nongnu.org; Tue, 18 Mar 2014 18:24:21 -0400 Received: from mail-qa0-x230.google.com ([2607:f8b0:400d:c00::230]:59145) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQ2Qh-0007nC-J0 for qemu-devel@nongnu.org; Tue, 18 Mar 2014 18:24:15 -0400 Received: by mail-qa0-f48.google.com with SMTP id m5so7659425qaj.7 for ; Tue, 18 Mar 2014 15:24:15 -0700 (PDT) Sender: Richard Henderson Message-ID: <5328C78B.7020202@twiddle.net> Date: Tue, 18 Mar 2014 15:24:11 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1395178235-29056-1-git-send-email-rth@twiddle.net> <1395178235-29056-4-git-send-email-rth@twiddle.net> In-Reply-To: <1395178235-29056-4-git-send-email-rth@twiddle.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 3/4] tcg: Mask shift counts to avoid undefined behavior List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Stefan Weil Gah. Description should have been "tci" and cc'd the maintainer. r~ On 03/18/2014 02:30 PM, Richard Henderson wrote: > TCG now requires unspecified behavior rather than a potential crash, > bring the C shift within the letter of the law. > > Signed-off-by: Richard Henderson > --- > tci.c | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/tci.c b/tci.c > index 0202ed9..6523ab8 100644 > --- a/tci.c > +++ b/tci.c > @@ -669,32 +669,32 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) > t0 = *tb_ptr++; > t1 = tci_read_ri32(&tb_ptr); > t2 = tci_read_ri32(&tb_ptr); > - tci_write_reg32(t0, t1 << t2); > + tci_write_reg32(t0, t1 << (t2 & 31)); > break; > case INDEX_op_shr_i32: > t0 = *tb_ptr++; > t1 = tci_read_ri32(&tb_ptr); > t2 = tci_read_ri32(&tb_ptr); > - tci_write_reg32(t0, t1 >> t2); > + tci_write_reg32(t0, t1 >> (t2 & 31)); > break; > case INDEX_op_sar_i32: > t0 = *tb_ptr++; > t1 = tci_read_ri32(&tb_ptr); > t2 = tci_read_ri32(&tb_ptr); > - tci_write_reg32(t0, ((int32_t)t1 >> t2)); > + tci_write_reg32(t0, ((int32_t)t1 >> (t2 & 31))); > break; > #if TCG_TARGET_HAS_rot_i32 > case INDEX_op_rotl_i32: > t0 = *tb_ptr++; > t1 = tci_read_ri32(&tb_ptr); > t2 = tci_read_ri32(&tb_ptr); > - tci_write_reg32(t0, rol32(t1, t2)); > + tci_write_reg32(t0, rol32(t1, t2 & 31)); > break; > case INDEX_op_rotr_i32: > t0 = *tb_ptr++; > t1 = tci_read_ri32(&tb_ptr); > t2 = tci_read_ri32(&tb_ptr); > - tci_write_reg32(t0, ror32(t1, t2)); > + tci_write_reg32(t0, ror32(t1, t2 & 31)); > break; > #endif > #if TCG_TARGET_HAS_deposit_i32 > @@ -936,32 +936,32 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) > t0 = *tb_ptr++; > t1 = tci_read_ri64(&tb_ptr); > t2 = tci_read_ri64(&tb_ptr); > - tci_write_reg64(t0, t1 << t2); > + tci_write_reg64(t0, t1 << (t2 & 63)); > break; > case INDEX_op_shr_i64: > t0 = *tb_ptr++; > t1 = tci_read_ri64(&tb_ptr); > t2 = tci_read_ri64(&tb_ptr); > - tci_write_reg64(t0, t1 >> t2); > + tci_write_reg64(t0, t1 >> (t2 & 63)); > break; > case INDEX_op_sar_i64: > t0 = *tb_ptr++; > t1 = tci_read_ri64(&tb_ptr); > t2 = tci_read_ri64(&tb_ptr); > - tci_write_reg64(t0, ((int64_t)t1 >> t2)); > + tci_write_reg64(t0, ((int64_t)t1 >> (t2 & 63))); > break; > #if TCG_TARGET_HAS_rot_i64 > case INDEX_op_rotl_i64: > t0 = *tb_ptr++; > t1 = tci_read_ri64(&tb_ptr); > t2 = tci_read_ri64(&tb_ptr); > - tci_write_reg64(t0, rol64(t1, t2)); > + tci_write_reg64(t0, rol64(t1, t2 & 63)); > break; > case INDEX_op_rotr_i64: > t0 = *tb_ptr++; > t1 = tci_read_ri64(&tb_ptr); > t2 = tci_read_ri64(&tb_ptr); > - tci_write_reg64(t0, ror64(t1, t2)); > + tci_write_reg64(t0, ror64(t1, t2 & 63)); > break; > #endif > #if TCG_TARGET_HAS_deposit_i64 >