From: Stefan Weil <sw@weilnetz.de>
To: Richard Henderson <rth@twiddle.net>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: Re: [Qemu-devel] [PATCH v2 3/4] tcg: Mask shift counts to avoid undefined behavior
Date: Wed, 19 Mar 2014 07:21:55 +0100 [thread overview]
Message-ID: <53293783.3050509@weilnetz.de> (raw)
In-Reply-To: <1395178235-29056-4-git-send-email-rth@twiddle.net>
Am 18.03.2014 22:30, schrieb Richard Henderson:
> TCG now requires unspecified behavior rather than a potential crash,
> bring the C shift within the letter of the law.
I know that C does not define the result of some shift / rotate
operations, but I don't understand the sentence above. Why does TCG or
TCI require unspecified behaviour now? Where was or is a potential crash?
The modifications below won't harm, but make the TCG interpreter slower.
Are they (all) necessary? Are there test cases which fail with the old code?
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> tci.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/tci.c b/tci.c
> index 0202ed9..6523ab8 100644
> --- a/tci.c
> +++ b/tci.c
> @@ -669,32 +669,32 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
> t0 = *tb_ptr++;
> t1 = tci_read_ri32(&tb_ptr);
> t2 = tci_read_ri32(&tb_ptr);
> - tci_write_reg32(t0, t1 << t2);
> + tci_write_reg32(t0, t1 << (t2 & 31));
> break;
> case INDEX_op_shr_i32:
> t0 = *tb_ptr++;
> t1 = tci_read_ri32(&tb_ptr);
> t2 = tci_read_ri32(&tb_ptr);
> - tci_write_reg32(t0, t1 >> t2);
> + tci_write_reg32(t0, t1 >> (t2 & 31));
Right shifts of unsigned values with unsigned shift count are always
defined, aren't they? So masking for those cases should not be needed.
> break;
> case INDEX_op_sar_i32:
> t0 = *tb_ptr++;
> t1 = tci_read_ri32(&tb_ptr);
> t2 = tci_read_ri32(&tb_ptr);
> - tci_write_reg32(t0, ((int32_t)t1 >> t2));
> + tci_write_reg32(t0, ((int32_t)t1 >> (t2 & 31)));
> break;
> #if TCG_TARGET_HAS_rot_i32
> case INDEX_op_rotl_i32:
> t0 = *tb_ptr++;
> t1 = tci_read_ri32(&tb_ptr);
> t2 = tci_read_ri32(&tb_ptr);
> - tci_write_reg32(t0, rol32(t1, t2));
> + tci_write_reg32(t0, rol32(t1, t2 & 31));
What about other users of rol32?
> break;
> case INDEX_op_rotr_i32:
> t0 = *tb_ptr++;
> t1 = tci_read_ri32(&tb_ptr);
> t2 = tci_read_ri32(&tb_ptr);
> - tci_write_reg32(t0, ror32(t1, t2));
> + tci_write_reg32(t0, ror32(t1, t2 & 31));
> break;
> #endif
> #if TCG_TARGET_HAS_deposit_i32
> @@ -936,32 +936,32 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
> t0 = *tb_ptr++;
> t1 = tci_read_ri64(&tb_ptr);
> t2 = tci_read_ri64(&tb_ptr);
> - tci_write_reg64(t0, t1 << t2);
> + tci_write_reg64(t0, t1 << (t2 & 63));
> break;
> case INDEX_op_shr_i64:
> t0 = *tb_ptr++;
> t1 = tci_read_ri64(&tb_ptr);
> t2 = tci_read_ri64(&tb_ptr);
> - tci_write_reg64(t0, t1 >> t2);
> + tci_write_reg64(t0, t1 >> (t2 & 63));
> break;
> case INDEX_op_sar_i64:
> t0 = *tb_ptr++;
> t1 = tci_read_ri64(&tb_ptr);
> t2 = tci_read_ri64(&tb_ptr);
> - tci_write_reg64(t0, ((int64_t)t1 >> t2));
> + tci_write_reg64(t0, ((int64_t)t1 >> (t2 & 63)));
> break;
> #if TCG_TARGET_HAS_rot_i64
> case INDEX_op_rotl_i64:
> t0 = *tb_ptr++;
> t1 = tci_read_ri64(&tb_ptr);
> t2 = tci_read_ri64(&tb_ptr);
> - tci_write_reg64(t0, rol64(t1, t2));
> + tci_write_reg64(t0, rol64(t1, t2 & 63));
> break;
> case INDEX_op_rotr_i64:
> t0 = *tb_ptr++;
> t1 = tci_read_ri64(&tb_ptr);
> t2 = tci_read_ri64(&tb_ptr);
> - tci_write_reg64(t0, ror64(t1, t2));
> + tci_write_reg64(t0, ror64(t1, t2 & 63));
> break;
> #endif
> #if TCG_TARGET_HAS_deposit_i64
>
Regards
Stefan
next prev parent reply other threads:[~2014-03-19 6:22 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-18 21:30 [Qemu-devel] [PATCH v2 0/4] tcg: out of range shift behavior Richard Henderson
2014-03-18 21:30 ` [Qemu-devel] [PATCH v2 1/4] tcg: Use "unspecified behavior" for shifts Richard Henderson
2014-03-18 21:30 ` [Qemu-devel] [PATCH v2 2/4] tcg: Mask shift quantities while folding Richard Henderson
2014-03-18 22:11 ` Peter Maydell
2014-03-18 21:30 ` [Qemu-devel] [PATCH v2 3/4] tcg: Mask shift counts to avoid undefined behavior Richard Henderson
2014-03-18 22:24 ` Richard Henderson
2014-03-19 6:21 ` Stefan Weil [this message]
2014-03-19 10:11 ` Peter Maydell
2014-03-19 15:25 ` Richard Henderson
2014-03-19 15:59 ` Peter Maydell
2014-03-18 21:30 ` [Qemu-devel] [PATCH v2 4/4] tcg: Fix out of range shift in deposit optimizations Richard Henderson
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