From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51732) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQOjs-0000O5-MN for qemu-devel@nongnu.org; Wed, 19 Mar 2014 18:13:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WQOjn-00035C-0d for qemu-devel@nongnu.org; Wed, 19 Mar 2014 18:13:32 -0400 Received: from mail-qc0-x22b.google.com ([2607:f8b0:400d:c01::22b]:49803) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQOjm-000358-SO for qemu-devel@nongnu.org; Wed, 19 Mar 2014 18:13:26 -0400 Received: by mail-qc0-f171.google.com with SMTP id c9so4871047qcz.30 for ; Wed, 19 Mar 2014 15:13:26 -0700 (PDT) Sender: Richard Henderson Message-ID: <532A1682.1070703@twiddle.net> Date: Wed, 19 Mar 2014 15:13:22 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1394836210-15934-1-git-send-email-rth@twiddle.net> <532A0650.3040109@twiddle.net> <532A087A.8060801@suse.de> In-Reply-To: <532A087A.8060801@suse.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH] cpu: Move tcg_exit_req to the end of CPUState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= , qemu-devel@nongnu.org On 03/19/2014 02:13 PM, Andreas Färber wrote: > Am 19.03.2014 22:04, schrieb Richard Henderson: >> Ping? This is a significant TCG code size regression >> for ARM, AArch64, and Sparc hosts. It helps x86 too, >> though that's not as severe. > > Sorry, applied to qom-cpu now: > https://github.com/afaerber/qemu-cpu/commits/qom-cpu > > How did you find this? Was there some assertion on one target, or do you > have some analysis code that you could share? No assertions; all of the targets worked. I was just reading asm_out dumps as I improved the Sparc backend. We went from beginning with 0x40000000: ld [ %i0 + -76 ], %l0 to 0x40000000: sethi %hi(0xffffbc00), %g1 0x40000004: or %g1, 0x2ec, %g1 ! 0xffffbeec 0x40000008: ld [ %i0 + %g1 ], %l0 That constant is of course -16660, out of range of the 13-bit signed addend. Then I got to thinking: ARM also has a 13-bit range (though in a silly 1's compliment form), AArch64 has an 8-bit signed addend, and i386 can use a smaller encoding for an 8-bit signed addend. So it could benefit just about all of the backends to keep this offset relatively small. r~