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[98.147.55.211]) by smtp.gmail.com with ESMTPSA id n4-20020a170902968400b001db8145a1a2sm11074557plp.274.2024.03.05.13.42.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 05 Mar 2024 13:42:33 -0800 (PST) Message-ID: <532d9634-ac02-4cb5-86a0-c09d723cd65b@linaro.org> Date: Tue, 5 Mar 2024 11:42:31 -1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v6 08/23] target/arm: Handle IS/FS in ISR_EL1 for NMI Content-Language: en-US To: Jinjie Ruan , peter.maydell@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20240305070331.2151131-1-ruanjinjie@huawei.com> <20240305070331.2151131-9-ruanjinjie@huawei.com> From: Richard Henderson In-Reply-To: <20240305070331.2151131-9-ruanjinjie@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/4/24 21:03, Jinjie Ruan via wrote: > Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or > CPU_INTERRUPT_VNMI, both CPSR_I and ISR_IS must be set. With > CPU_INTERRUPT_VFIQ and HCRX_EL2.VFNMI set, both CPSR_F and ISR_FS must be set. > > Signed-off-by: Jinjie Ruan > --- > v6: > - Verify that HCR_EL2.VF is set before checking VFNMI. > v4； > - Also handle VNMI. > v3: > - CPU_INTERRUPT_NMI do not set FIQ, so remove it. > - With CPU_INTERRUPT_NMI, both CPSR_I and ISR_IS must be set. > --- > target/arm/cpu.h | 2 ++ > target/arm/helper.c | 14 ++++++++++++++ > 2 files changed, 16 insertions(+) Reviewed-by: Richard Henderson r~