Re: [Qemu-devel] [PATCH 01/26] tcg-aarch64: Properly detect SIGSEGV writes

[Richard Henderson <rth@twiddle.net>]

On 03/24/2014 05:41 AM, Peter Maydell wrote:
> On 15 March 2014 02:48, Richard Henderson <rth@twiddle.net> wrote:
>> Since the kernel doesn't pass any info on the reason for the fault,
>> disassemble the instruction to detect a store.
> 
> Incidentally, I've been wondering if we could improve
> handle_cpu_signal so that at least the "check if this
> fault was because we write-protected a page when we
> translated code out of it" part doesn't depend on the
> CPU-specific signal handler setting is_write correctly.
> I think most guests don't depend on getting exactly
> correct fault information, but if we don't track our
> own page protection correctly then even simple guest
> binaries don't work.

Indeed.  I had wondered if just setting is_write=1 when we don't know wouldn't
be a better solution that what we have now.

> (Also, shouldn't we ideally speaking see if the SIGSEGV
> was the result of attempting to execute from non-executable
> memory?)

Probably, but I'm not sure we know at this point.

Although, honestly, the best fallback would be softmmu.  Which we really ought
to enable for both 64-on-32 and host > guest page size.  Especially with the
later we sometimes can't even *load* simple binaries.


r~