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From: Tom Musta <tommusta@gmail.com>
To: "Andreas Färber" <afaerber@suse.de>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Anton Blanchard" <anton@samba.org>
Cc: clg@fr.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	gkurz@linux.vnet.ibm.com
Subject: Re: [Qemu-devel] [PATCH 1/6] target-ppc: POWER8 supports the MSR_LE bit
Date: Thu, 27 Mar 2014 12:10:29 -0500	[thread overview]
Message-ID: <53345B85.3090501@gmail.com> (raw)
In-Reply-To: <53343C80.5060708@suse.de>

On 3/27/2014 9:58 AM, Andreas Färber wrote:
> Am 25.03.2014 08:29, schrieb Alex Bennée:
>>
>> Anton Blanchard <anton@samba.org> writes:
>>
>>> Add MSR_LE to the msr_mask for POWER8.
>>>
>> <snip>
>>> -    pcc->msr_mask = 0x800000000284FF36ULL;
>>> +    pcc->msr_mask = 0x800000000284FF37ULL;
>> <snip>
>>
>> Should we be adding some #define's for the various bit positions on this
>> mask? Looking at the current code it looks like a big ream of magic
>> numbers.
> 
> In general I concur that defines would be nice, however for 2.0 that's
> too risky for me as temporary maintainer and I'm not sure if these
> values are being pieced together by contributors or whether this is
> coming directly from the manual?

There are defines in target-ppc/cpu.h that identify the bit position.  So
something like this could/should be done (in 2.1):

    pcc->msr_mask =
        (1ULL << MSR_SF) |
        (1ULL << MSR_TAG) |
        (1ULL << MSR_ISF) |
        (1ULL << MSR_DR /* MISSING */ ) |
        (1ULL << MSR_IR /* MISSING */ ) |
        (1ULL << MSR_FE1 /* MISSING */ ) |
        (1ULL << MSR_BE /* MISSING */ ) |
        (1ULL << MSR_ME /* MISSING */ ) |
        (1ULL << MSR_SE /* MISSING */ ) |
        (1ULL << MSR_FE0 /* MISSING */ ) |
        (1ULL << MSR_FP /* MISSING */ ) |
        (1ULL << MSR_PR /* MISSING */ ) |
        (1ULL << MSR_EE /* MISSING */ );

The set of defines is incomplete -- the items marked MISSING are not currently there.
They could, of course, easily be added.

Unfortunately, this behavior has been repeated over 50 times in the target-ppc/translate_init.c
file and some MSR bit positions have multiple meanings based on processor family and era.  So
a thorough and accurate cleanup would provide a nice challenge :)

I'm willing to tackle this after I get done with some decimal floating point work (probably 2
weeks).

> The other issue has been that adding a new family, even after the
> initial round of cleanups, still requires a chunk of code to be copied,
> which seems prone to forgetting little bits on the new one, then maybe
> fixing up the original template but not the derived models, etc.

  reply	other threads:[~2014-03-27 17:11 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-03-25  2:40 [Qemu-devel] [PATCH 1/6] target-ppc: POWER8 supports the MSR_LE bit Anton Blanchard
2014-03-25  2:40 ` [Qemu-devel] [PATCH 2/6] target-ppc: POWER8 supports isel Anton Blanchard
2014-03-25  2:40 ` [Qemu-devel] [PATCH 3/6] target-ppc: POWER7+ supports the MSR_VSX bit Anton Blanchard
2014-03-25  2:40 ` [Qemu-devel] [PATCH 4/6] target-ppc: MSR_POW not supported on POWER7/7+/8 Anton Blanchard
2014-03-25  2:40 ` [Qemu-devel] [PATCH 5/6] target-ppc: Fix Book3S PMU SPRs Anton Blanchard
2014-04-10 13:22   ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-03-25  2:40 ` [Qemu-devel] [PATCH 6/6] target-ppc: Add PMC7/8 to 970 Anton Blanchard
2014-03-27 13:03   ` [Qemu-devel] [Qemu-ppc] " Alexey Kardashevskiy
2014-03-27 15:40     ` Andreas Färber
2014-04-10 13:24   ` Alexander Graf
2014-03-25  7:29 ` [Qemu-devel] [PATCH 1/6] target-ppc: POWER8 supports the MSR_LE bit Alex Bennée
2014-03-27 14:58   ` Andreas Färber
2014-03-27 17:10     ` Tom Musta [this message]
2014-03-27 15:36 ` Andreas Färber

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