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Date: Thu, 03 Apr 2014 20:50:32 +0200
From: =?ISO-8859-15?Q?Andreas_F=E4rber?= <afaerber@suse.de>
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Subject: Re: [Qemu-devel] [PATCH 2.0] PPC: E500: Set PIR default reset value
 rather than SPR value
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To: Alexander Graf <agraf@suse.de>, qemu-devel@nongnu.org
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>, Peter Maydell <peter.maydell@linaro.org>, Greg Kurz <gkurz@linux.vnet.ibm.com>, qemu-ppc@nongnu.org, Frederic Konrad <fred.konrad@greensocs.com>

Am 03.04.2014 20:48, schrieb Alexander Graf:
> We now reset SPRs to their reset values on CPU reset. So if we want
> to have an SPR persistently changed, we need to change its default
> reset value rather than the value itself manually.
>=20
> Do this for SPR_BOOKE_PIR, fixing e500v2 SMP boot.
>=20
> Reported-by: Frederic Konrad <fred.konrad@greensocs.com>

Suggested-by: Andreas F=E4rber <afaerber@suse.de>

> Signed-off-by: Alexander Graf <agraf@suse.de>
> ---
>  hw/ppc/e500.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
> index d7ba25f..f984b3e 100644
> --- a/hw/ppc/e500.c
> +++ b/hw/ppc/e500.c
> @@ -649,7 +649,7 @@ void ppce500_init(QEMUMachineInitArgs *args, PPCE50=
0Params *params)
>          input =3D (qemu_irq *)env->irq_inputs;
>          irqs[i][OPENPIC_OUTPUT_INT] =3D input[PPCE500_INPUT_INT];
>          irqs[i][OPENPIC_OUTPUT_CINT] =3D input[PPCE500_INPUT_CINT];
> -        env->spr[SPR_BOOKE_PIR] =3D cs->cpu_index =3D i;
> +        env->spr_cb[SPR_BOOKE_PIR].default_value =3D cs->cpu_index =3D=
 i;
>          env->mpic_iack =3D MPC8544_CCSRBAR_BASE +
>                           MPC8544_MPIC_REGS_OFFSET + 0xa0;
> =20

.default_value then. ;)

Andreas

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