From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41521) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WVrya-0005ip-MX for qemu-devel@nongnu.org; Thu, 03 Apr 2014 20:27:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WVryV-0007dc-U0 for qemu-devel@nongnu.org; Thu, 03 Apr 2014 20:27:20 -0400 Received: from mail-pd0-f171.google.com ([209.85.192.171]:33087) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WVryV-0007bW-O9 for qemu-devel@nongnu.org; Thu, 03 Apr 2014 20:27:15 -0400 Received: by mail-pd0-f171.google.com with SMTP id r10so2516758pdi.16 for ; Thu, 03 Apr 2014 17:27:14 -0700 (PDT) Message-ID: <533DFC52.7080702@ozlabs.ru> Date: Fri, 04 Apr 2014 11:26:58 +1100 From: Alexey Kardashevskiy MIME-Version: 1.0 References: <1396550899-26024-1-git-send-email-agraf@suse.de> <08A36590-DD30-4F2F-83A9-CA5B403DBFF6@suse.de> In-Reply-To: <08A36590-DD30-4F2F-83A9-CA5B403DBFF6@suse.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 2.0] PPC: E500: Set PIR default reset value rather than SPR value List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf , Peter Maydell Cc: Frederic Konrad , "qemu-ppc@nongnu.org" , QEMU Developers , Greg Kurz , =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= On 04/04/2014 05:58 AM, Alexander Graf wrote: > > On 03.04.2014, at 20:55, Peter Maydell wrote: > >> On 3 April 2014 19:48, Alexander Graf wrote: >>> We now reset SPRs to their reset values on CPU reset. So if we want >>> to have an SPR persistently changed, we need to change its default >>> reset value rather than the value itself manually. >>> >>> Do this for SPR_BOOKE_PIR, fixing e500v2 SMP boot. >>> >>> Reported-by: Frederic Konrad >>> Signed-off-by: Alexander Graf >>> --- >>> hw/ppc/e500.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c >>> index d7ba25f..f984b3e 100644 >>> --- a/hw/ppc/e500.c >>> +++ b/hw/ppc/e500.c >>> @@ -649,7 +649,7 @@ void ppce500_init(QEMUMachineInitArgs *args, PPCE500Params *params) >>> input = (qemu_irq *)env->irq_inputs; >>> irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; >>> irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; >>> - env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i; >>> + env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; >> >> Not an issue introduced with this patch, but should we really >> be missing with CPUState::cpu_index in a board file? >> (Nowhere else does, it's otherwise simply set to an >> appropriately incremented index by cpu_exec_init().) >> I rather suspect that cpu_index will already be set >> to the value we set it, in any case... > > Most likely, but I'd rather not touch that logic for 2.0 :) git grep "cpu_index\s\+=[^=]": cpus.c:1404: cpu_index = 0; exec.c:482: cpu_index = 0; exec.c:486: cpu->cpu_index = cpu_index; hmp.c:742: cpu_index = qdict_get_int(qdict, "index"); hw/ppc/e500.c:652: env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i; monitor.c:2225: int cpu_index = qdict_get_int(qdict, "cpu_index"); scripts/qmp/qmp-shell:183: self.__cpu_index = 0 scripts/qmp/qmp-shell:216: def __cmd_passthrough(self, cmdline, cpu_index = 0): scripts/qmp/qmp-shell:229: self.__cpu_index = idx Assigning cpu_index in e500.c looks to me as a strange idea. And it is hidden so nicely with two "=" in a row :-/ Out of curiosity - in the real e500 hardware, PIR does not get reset on CPU reset? -- Alexey