From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38235) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wjkyn-0008Qa-E8 for qemu-devel@nongnu.org; Mon, 12 May 2014 03:49:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wjkyh-0002EY-CP for qemu-devel@nongnu.org; Mon, 12 May 2014 03:48:57 -0400 Received: from cantor2.suse.de ([195.135.220.15]:46743 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wjkyh-0002ET-6b for qemu-devel@nongnu.org; Mon, 12 May 2014 03:48:51 -0400 Message-ID: <53707CE1.6010500@suse.de> Date: Mon, 12 May 2014 09:48:49 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1399041202-26184-1-git-send-email-pbonzini@redhat.com> <1399041202-26184-8-git-send-email-pbonzini@redhat.com> In-Reply-To: <1399041202-26184-8-git-send-email-pbonzini@redhat.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 7/8] pc: port 92 reset requires a low->high transition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org Am 02.05.2014 16:33, schrieb Paolo Bonzini: > The PIIX datasheet says that "before another INIT pulse can be > generated via [port 92h], [bit 0] must be written back to a > zero. >=20 > This bug is masked right now because a full reset will clear the > value of port 92h. But once we implement soft reset correctly, > the next attempt to enable the A20 line by setting bit 1 (and > leaving the others untouched) will cause another reset. >=20 > Reviewed-by: Anthony Liguori > Signed-off-by: Paolo Bonzini Reviewed-by: Andreas F=E4rber Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg