* [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files
@ 2014-05-08 16:09 Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 01/11] hw: use ld_p/st_p instead of ld_raw/st_raw Paolo Bonzini
` (11 more replies)
0 siblings, 12 replies; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-08 16:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
This series is a prerequisite for improving the SMAP emulation in
qemu-system-x86_64. SMAP is a Broadwell feature and testing it in the
kernel is probably the #1 reason why people are using TCG x86 nowadays.
In order to implement some of the SMAP checks correctly, I need to define
a new set of ld/st functions, similar to ldl_data but with a different
definition of cpu_mmu_index. This series lets me do that painlessly,
by simplifying the set of macros expected by softmmu_header.h. This is
done by patches 2 to 4.
In addition, implementation of the MMU lookups are spread across all C
files. There is no reason for this, it can be done in cputlb.c directly.
This is done by patches 5 to 7.
CPU load/store functions are also split around multiple headers: tcg/tcg.h,
softmmu_header.h, cpu-all.h, exec-all.h. This series consolidates them
all in a single header, cpu_ldst.h, in patches 8 to 11.
The only reason why this is RFC is that it depends on TCG backends
stopping their use of helper_ld*_mmu and using instead the new
"return-address aware" helpers. With this conversion done, helper_ld*_mmu
are not anymore TCG-related and it makes sense to move them to cpu_ldst.h.
The only backends left to convert are S390, with patches on the list,
and MIPS, which should also get done for 2.1.
Paolo
Paolo Bonzini (11):
hw: use ld_p/st_p instead of ld_raw/st_raw
softmmu: start introducing SOFTMMU_CODE_ACCESS in softmmu_header.h
softmmu: move MMUSUFFIX under SOFTMMU_CODE_ACCESS
softmmu: move definition of CPU_MMU_INDEX to inclusion site, drop ACCESS_TYPE
softmmu: move ALIGNED_ONLY to cpu.h
softmmu: commonize helper definitions
softmmu: move softmmu_template.h out of include/
softmmu: make do_unaligned_access extern
target-arm: move arm_*_code to a separate file
softmmu: introduce cpu_ldst.h
softmmu: move all load/store functions to cpu_ldst.h
bsd-user/qemu.h | 1 +
cputlb.c | 27 +-
hw/9pfs/virtio-9p-device.c | 2 +-
hw/arm/nseries.c | 236 ++++++------
hw/block/virtio-blk.c | 12 +-
hw/display/omap_lcd_template.h | 10 +-
hw/display/sm501_template.h | 6 +-
hw/display/vga_template.h | 4 +-
hw/mips/mips_fulong2e.c | 28 +-
hw/mips/mips_malta.c | 176 ++++-----
hw/scsi/vhost-scsi.c | 4 +-
hw/scsi/virtio-scsi.c | 28 +-
include/exec/cpu-all.h | 119 ------
include/exec/cpu_ldst.h | 400 +++++++++++++++++++++
.../exec/{softmmu_header.h => cpu_ldst_template.h} | 32 +-
include/exec/exec-all.h | 23 --
include/exec/softmmu_exec.h | 216 -----------
linux-user/qemu.h | 1 +
monitor.c | 1 +
.../exec/softmmu_template.h => softmmu_template.h | 2 +
target-alpha/cpu.h | 4 +
target-alpha/mem_helper.c | 23 +-
target-alpha/translate.c | 1 +
target-arm/arm_ldst.h | 48 +++
target-arm/cpu.h | 22 --
target-arm/helper.c | 1 +
target-arm/op_helper.c | 17 +-
target-arm/translate-a64.c | 1 +
target-arm/translate.c | 1 +
target-cris/helper.c | 1 +
target-cris/op_helper.c | 17 +-
target-cris/translate.c | 1 +
target-i386/fpu_helper.c | 5 +-
target-i386/mem_helper.c | 23 +-
target-i386/misc_helper.c | 5 +-
target-i386/seg_helper.c | 5 +-
target-i386/svm_helper.c | 5 +-
target-i386/translate.c | 1 +
target-lm32/op_helper.c | 12 +-
target-lm32/translate.c | 1 +
target-m68k/op_helper.c | 17 +-
target-m68k/translate.c | 1 +
target-microblaze/op_helper.c | 12 +-
target-microblaze/translate.c | 1 +
target-mips/cpu.h | 4 +
target-mips/op_helper.c | 28 +-
target-mips/translate.c | 1 +
target-moxie/helper.c | 16 +-
target-moxie/translate.c | 1 +
target-openrisc/mmu_helper.c | 15 +-
target-openrisc/translate.c | 1 +
target-ppc/excp_helper.c | 1 +
target-ppc/mem_helper.c | 5 +-
target-ppc/mmu_helper.c | 17 +-
target-ppc/translate.c | 1 +
target-s390x/fpu_helper.c | 5 +-
target-s390x/helper.c | 1 +
target-s390x/mem_helper.c | 16 +-
target-s390x/misc_helper.c | 2 +-
target-s390x/translate.c | 1 +
target-sh4/op_helper.c | 16 +-
target-sh4/translate.c | 1 +
target-sparc/cpu.h | 6 +
target-sparc/ldst_helper.c | 28 +-
target-sparc/translate.c | 1 +
target-unicore32/op_helper.c | 17 +-
target-unicore32/translate.c | 1 +
target-xtensa/cpu.h | 4 +
target-xtensa/op_helper.c | 23 +-
target-xtensa/translate.c | 1 +
tcg/tcg.h | 13 -
tci.c | 1 +
user-exec.c | 1 +
73 files changed, 806 insertions(+), 975 deletions(-)
create mode 100644 include/exec/cpu_ldst.h
rename include/exec/{softmmu_header.h => cpu_ldst_template.h} (89%)
delete mode 100644 include/exec/softmmu_exec.h
rename include/exec/softmmu_template.h => softmmu_template.h (99%)
create mode 100644 target-arm/arm_ldst.h
--
1.8.3.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Qemu-devel] [RFC PATCH 01/11] hw: use ld_p/st_p instead of ld_raw/st_raw
2014-05-08 16:09 [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Paolo Bonzini
@ 2014-05-08 16:09 ` Paolo Bonzini
2014-05-09 18:18 ` Peter Maydell
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 02/11] softmmu: start introducing SOFTMMU_CODE_ACCESS in softmmu_header.h Paolo Bonzini
` (10 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-08 16:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
The ld_raw and st_raw definitions are only needed in code that
must compile for both user-mode and softmmu emulation. Device
models can use the equivalent ld_p/st_p which are simple
pointer accessors.
The checkpatch situation of nseries.c and mips_malta.c is
messy. I'm only doing a textual substitution in this RFC,
maintainers should let me know what they prefer.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/9pfs/virtio-9p-device.c | 2 +-
hw/arm/nseries.c | 236 ++++++++++++++++++++---------------------
hw/block/virtio-blk.c | 12 +--
hw/display/omap_lcd_template.h | 10 +-
hw/display/sm501_template.h | 6 +-
hw/display/vga_template.h | 4 +-
hw/mips/mips_fulong2e.c | 28 ++---
hw/mips/mips_malta.c | 176 +++++++++++++++---------------
hw/scsi/vhost-scsi.c | 4 +-
hw/scsi/virtio-scsi.c | 28 ++---
10 files changed, 253 insertions(+), 253 deletions(-)
diff --git a/hw/9pfs/virtio-9p-device.c b/hw/9pfs/virtio-9p-device.c
index 15a4983..653762a 100644
--- a/hw/9pfs/virtio-9p-device.c
+++ b/hw/9pfs/virtio-9p-device.c
@@ -34,7 +34,7 @@ static void virtio_9p_get_config(VirtIODevice *vdev, uint8_t *config)
len = strlen(s->tag);
cfg = g_malloc0(sizeof(struct virtio_9p_config) + len);
- stw_raw(&cfg->tag_len, len);
+ stw_p(&cfg->tag_len, len);
/* We don't copy the terminating null to config space */
memcpy(cfg->tag, s->tag, len);
memcpy(config, cfg, s->config_size);
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index c28f895..ec43f51 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -834,118 +834,118 @@ static void n800_setup_nolo_tags(void *sram_base)
strcpy((void *) (p + 8), "F5");
- stl_raw(p + 10, 0x04f70000);
+ stl_p(p + 10, 0x04f70000);
strcpy((void *) (p + 9), "RX-34");
/* RAM size in MB? */
- stl_raw(p + 12, 0x80);
+ stl_p(p + 12, 0x80);
/* Pointer to the list of tags */
- stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
+ stl_p(p + 13, OMAP2_SRAM_BASE + 0x9000);
/* The NOLO tags start here */
p = sram_base + 0x9000;
#define ADD_TAG(tag, len) \
- stw_raw((uint16_t *) p + 0, tag); \
- stw_raw((uint16_t *) p + 1, len); p ++; \
- stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
+ stw_p((uint16_t *) p + 0, tag); \
+ stw_p((uint16_t *) p + 1, len); p ++; \
+ stl_p(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
/* OMAP STI console? Pin out settings? */
ADD_TAG(0x6e01, 414);
for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++)
- stl_raw(v ++, n800_pinout[i]);
+ stl_p(v ++, n800_pinout[i]);
/* Kernel memsize? */
ADD_TAG(0x6e05, 1);
- stl_raw(v ++, 2);
+ stl_p(v ++, 2);
/* NOLO serial console */
ADD_TAG(0x6e02, 4);
- stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
+ stl_p(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
#if 0
/* CBUS settings (Retu/AVilma) */
ADD_TAG(0x6e03, 6);
- stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
- stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
- stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
+ stw_p((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
+ stw_p((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
+ stw_p((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
v += 2;
#endif
/* Nokia ASIC BB5 (Retu/Tahvo) */
ADD_TAG(0x6e0a, 4);
- stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
- stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
+ stw_p((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
+ stw_p((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
v ++;
/* LCD console? */
ADD_TAG(0x6e04, 4);
- stw_raw((uint16_t *) v + 0, 30); /* ??? */
- stw_raw((uint16_t *) v + 1, 24); /* ??? */
+ stw_p((uint16_t *) v + 0, 30); /* ??? */
+ stw_p((uint16_t *) v + 1, 24); /* ??? */
v ++;
#if 0
/* LCD settings */
ADD_TAG(0x6e06, 2);
- stw_raw((uint16_t *) (v ++), 15); /* ??? */
+ stw_p((uint16_t *) (v ++), 15); /* ??? */
#endif
/* I^2C (Menelaus) */
ADD_TAG(0x6e07, 4);
- stl_raw(v ++, 0x00720000); /* ??? */
+ stl_p(v ++, 0x00720000); /* ??? */
/* Unknown */
ADD_TAG(0x6e0b, 6);
- stw_raw((uint16_t *) v + 0, 94); /* ??? */
- stw_raw((uint16_t *) v + 1, 23); /* ??? */
- stw_raw((uint16_t *) v + 2, 0); /* ??? */
+ stw_p((uint16_t *) v + 0, 94); /* ??? */
+ stw_p((uint16_t *) v + 1, 23); /* ??? */
+ stw_p((uint16_t *) v + 2, 0); /* ??? */
v += 2;
/* OMAP gpio switch info */
ADD_TAG(0x6e0c, 80);
strcpy((void *) v, "bat_cover"); v += 3;
- stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
- stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
+ stw_p((uint16_t *) v + 0, 110); /* GPIO num ??? */
+ stw_p((uint16_t *) v + 1, 1); /* GPIO num ??? */
v += 2;
strcpy((void *) v, "cam_act"); v += 3;
- stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
- stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
+ stw_p((uint16_t *) v + 0, 95); /* GPIO num ??? */
+ stw_p((uint16_t *) v + 1, 32); /* GPIO num ??? */
v += 2;
strcpy((void *) v, "cam_turn"); v += 3;
- stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
- stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
+ stw_p((uint16_t *) v + 0, 12); /* GPIO num ??? */
+ stw_p((uint16_t *) v + 1, 33); /* GPIO num ??? */
v += 2;
strcpy((void *) v, "headphone"); v += 3;
- stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
- stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
+ stw_p((uint16_t *) v + 0, 107); /* GPIO num ??? */
+ stw_p((uint16_t *) v + 1, 17); /* GPIO num ??? */
v += 2;
/* Bluetooth */
ADD_TAG(0x6e0e, 12);
- stl_raw(v ++, 0x5c623d01); /* ??? */
- stl_raw(v ++, 0x00000201); /* ??? */
- stl_raw(v ++, 0x00000000); /* ??? */
+ stl_p(v ++, 0x5c623d01); /* ??? */
+ stl_p(v ++, 0x00000201); /* ??? */
+ stl_p(v ++, 0x00000000); /* ??? */
/* CX3110x WLAN settings */
ADD_TAG(0x6e0f, 8);
- stl_raw(v ++, 0x00610025); /* ??? */
- stl_raw(v ++, 0xffff0057); /* ??? */
+ stl_p(v ++, 0x00610025); /* ??? */
+ stl_p(v ++, 0xffff0057); /* ??? */
/* MMC host settings */
ADD_TAG(0x6e10, 12);
- stl_raw(v ++, 0xffff000f); /* ??? */
- stl_raw(v ++, 0xffffffff); /* ??? */
- stl_raw(v ++, 0x00000060); /* ??? */
+ stl_p(v ++, 0xffff000f); /* ??? */
+ stl_p(v ++, 0xffffffff); /* ??? */
+ stl_p(v ++, 0x00000060); /* ??? */
/* OneNAND chip select */
ADD_TAG(0x6e11, 10);
- stl_raw(v ++, 0x00000401); /* ??? */
- stl_raw(v ++, 0x0002003a); /* ??? */
- stl_raw(v ++, 0x00000002); /* ??? */
+ stl_p(v ++, 0x00000401); /* ??? */
+ stl_p(v ++, 0x0002003a); /* ??? */
+ stl_p(v ++, 0x00000002); /* ??? */
/* TEA5761 sensor settings */
ADD_TAG(0x6e12, 2);
- stl_raw(v ++, 93); /* GPIO num ??? */
+ stl_p(v ++, 93); /* GPIO num ??? */
#if 0
/* Unknown tag */
@@ -956,8 +956,8 @@ static void n800_setup_nolo_tags(void *sram_base)
#endif
/* End of the list */
- stl_raw(p ++, 0x00000000);
- stl_raw(p ++, 0x00000000);
+ stl_p(p ++, 0x00000000);
+ stl_p(p ++, 0x00000000);
}
/* This task is normally performed by the bootloader. If we're loading
@@ -1119,112 +1119,112 @@ static int n8x0_atag_setup(void *p, int model)
w = p;
- stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
- stw_raw(w ++, 4); /* u16 len */
- stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
+ stw_p(w ++, OMAP_TAG_UART); /* u16 tag */
+ stw_p(w ++, 4); /* u16 len */
+ stw_p(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
w ++;
#if 0
- stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
- stw_raw(w ++, 4); /* u16 len */
- stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
- stw_raw(w ++, 115200); /* u32 console_speed */
+ stw_p(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
+ stw_p(w ++, 4); /* u16 len */
+ stw_p(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
+ stw_p(w ++, 115200); /* u32 console_speed */
#endif
- stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
- stw_raw(w ++, 36); /* u16 len */
+ stw_p(w ++, OMAP_TAG_LCD); /* u16 tag */
+ stw_p(w ++, 36); /* u16 len */
strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
w += 8;
strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
w += 8;
- stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
- stw_raw(w ++, 24); /* u8 data_lines */
-
- stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
- stw_raw(w ++, 8); /* u16 len */
- stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
- stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
- stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
+ stw_p(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
+ stw_p(w ++, 24); /* u8 data_lines */
+
+ stw_p(w ++, OMAP_TAG_CBUS); /* u16 tag */
+ stw_p(w ++, 8); /* u16 len */
+ stw_p(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
+ stw_p(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
+ stw_p(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
w ++;
- stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
- stw_raw(w ++, 4); /* u16 len */
- stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
- stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
+ stw_p(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
+ stw_p(w ++, 4); /* u16 len */
+ stw_p(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
+ stw_p(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
for (; gpiosw->name; gpiosw ++) {
- stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
- stw_raw(w ++, 20); /* u16 len */
+ stw_p(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
+ stw_p(w ++, 20); /* u16 len */
strcpy((void *) w, gpiosw->name); /* char name[12] */
w += 6;
- stw_raw(w ++, gpiosw->line); /* u16 gpio */
- stw_raw(w ++, gpiosw->type);
- stw_raw(w ++, 0);
- stw_raw(w ++, 0);
+ stw_p(w ++, gpiosw->line); /* u16 gpio */
+ stw_p(w ++, gpiosw->type);
+ stw_p(w ++, 0);
+ stw_p(w ++, 0);
}
- stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
- stw_raw(w ++, 12); /* u16 len */
+ stw_p(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
+ stw_p(w ++, 12); /* u16 len */
b = (void *) w;
- stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
- stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
- stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
- stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
- stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
+ stb_p(b ++, 0x01); /* u8 chip_type (CSR) */
+ stb_p(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
+ stb_p(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
+ stb_p(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
+ stb_p(b ++, BT_UART + 1); /* u8 bt_uart */
memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
b += 6;
- stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
+ stb_p(b ++, 0x02); /* u8 bt_sysclk (38.4) */
w = (void *) b;
- stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
- stw_raw(w ++, 8); /* u16 len */
- stw_raw(w ++, 0x25); /* u8 chip_type */
- stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
- stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
- stw_raw(w ++, -1); /* s16 spi_cs_gpio */
+ stw_p(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
+ stw_p(w ++, 8); /* u16 len */
+ stw_p(w ++, 0x25); /* u8 chip_type */
+ stw_p(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
+ stw_p(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
+ stw_p(w ++, -1); /* s16 spi_cs_gpio */
- stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
- stw_raw(w ++, 16); /* u16 len */
+ stw_p(w ++, OMAP_TAG_MMC); /* u16 tag */
+ stw_p(w ++, 16); /* u16 len */
if (model == 810) {
- stw_raw(w ++, 0x23f); /* unsigned flags */
- stw_raw(w ++, -1); /* s16 power_pin */
- stw_raw(w ++, -1); /* s16 switch_pin */
- stw_raw(w ++, -1); /* s16 wp_pin */
- stw_raw(w ++, 0x240); /* unsigned flags */
- stw_raw(w ++, 0xc000); /* s16 power_pin */
- stw_raw(w ++, 0x0248); /* s16 switch_pin */
- stw_raw(w ++, 0xc000); /* s16 wp_pin */
+ stw_p(w ++, 0x23f); /* unsigned flags */
+ stw_p(w ++, -1); /* s16 power_pin */
+ stw_p(w ++, -1); /* s16 switch_pin */
+ stw_p(w ++, -1); /* s16 wp_pin */
+ stw_p(w ++, 0x240); /* unsigned flags */
+ stw_p(w ++, 0xc000); /* s16 power_pin */
+ stw_p(w ++, 0x0248); /* s16 switch_pin */
+ stw_p(w ++, 0xc000); /* s16 wp_pin */
} else {
- stw_raw(w ++, 0xf); /* unsigned flags */
- stw_raw(w ++, -1); /* s16 power_pin */
- stw_raw(w ++, -1); /* s16 switch_pin */
- stw_raw(w ++, -1); /* s16 wp_pin */
- stw_raw(w ++, 0); /* unsigned flags */
- stw_raw(w ++, 0); /* s16 power_pin */
- stw_raw(w ++, 0); /* s16 switch_pin */
- stw_raw(w ++, 0); /* s16 wp_pin */
+ stw_p(w ++, 0xf); /* unsigned flags */
+ stw_p(w ++, -1); /* s16 power_pin */
+ stw_p(w ++, -1); /* s16 switch_pin */
+ stw_p(w ++, -1); /* s16 wp_pin */
+ stw_p(w ++, 0); /* unsigned flags */
+ stw_p(w ++, 0); /* s16 power_pin */
+ stw_p(w ++, 0); /* s16 switch_pin */
+ stw_p(w ++, 0); /* s16 wp_pin */
}
- stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
- stw_raw(w ++, 4); /* u16 len */
- stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
+ stw_p(w ++, OMAP_TAG_TEA5761); /* u16 tag */
+ stw_p(w ++, 4); /* u16 len */
+ stw_p(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
w ++;
partition = (model == 810) ? n810_part_info : n800_part_info;
for (; partition->name; partition ++) {
- stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
- stw_raw(w ++, 28); /* u16 len */
+ stw_p(w ++, OMAP_TAG_PARTITION); /* u16 tag */
+ stw_p(w ++, 28); /* u16 len */
strcpy((void *) w, partition->name); /* char name[16] */
l = (void *) (w + 8);
- stl_raw(l ++, partition->size); /* unsigned int size */
- stl_raw(l ++, partition->offset); /* unsigned int offset */
- stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
+ stl_p(l ++, partition->size); /* unsigned int size */
+ stl_p(l ++, partition->offset); /* unsigned int offset */
+ stl_p(l ++, partition->mask); /* unsigned int mask_flags */
w = (void *) l;
}
- stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
- stw_raw(w ++, 12); /* u16 len */
+ stw_p(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
+ stw_p(w ++, 12); /* u16 len */
#if 0
strcpy((void *) w, "por"); /* char reason_str[12] */
strcpy((void *) w, "charger"); /* char reason_str[12] */
@@ -1242,15 +1242,15 @@ static int n8x0_atag_setup(void *p, int model)
w += 6;
tag = (model == 810) ? "RX-44" : "RX-34";
- stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
- stw_raw(w ++, 24); /* u16 len */
+ stw_p(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
+ stw_p(w ++, 24); /* u16 len */
strcpy((void *) w, "product"); /* char component[12] */
w += 6;
strcpy((void *) w, tag); /* char version[12] */
w += 6;
- stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
- stw_raw(w ++, 24); /* u16 len */
+ stw_p(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
+ stw_p(w ++, 24); /* u16 len */
strcpy((void *) w, "hw-build"); /* char component[12] */
w += 6;
strcpy((void *) w, "QEMU ");
@@ -1258,8 +1258,8 @@ static int n8x0_atag_setup(void *p, int model)
w += 6;
tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
- stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
- stw_raw(w ++, 24); /* u16 len */
+ stw_p(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
+ stw_p(w ++, 24); /* u16 len */
strcpy((void *) w, "nolo"); /* char component[12] */
w += 6;
strcpy((void *) w, tag); /* char version[12] */
diff --git a/hw/block/virtio-blk.c b/hw/block/virtio-blk.c
index 8a568e5..b1fc1de 100644
--- a/hw/block/virtio-blk.c
+++ b/hw/block/virtio-blk.c
@@ -487,12 +487,12 @@ static void virtio_blk_update_config(VirtIODevice *vdev, uint8_t *config)
bdrv_get_geometry(s->bs, &capacity);
memset(&blkcfg, 0, sizeof(blkcfg));
- stq_raw(&blkcfg.capacity, capacity);
- stl_raw(&blkcfg.seg_max, 128 - 2);
- stw_raw(&blkcfg.cylinders, s->conf->cyls);
- stl_raw(&blkcfg.blk_size, blk_size);
- stw_raw(&blkcfg.min_io_size, s->conf->min_io_size / blk_size);
- stw_raw(&blkcfg.opt_io_size, s->conf->opt_io_size / blk_size);
+ stq_p(&blkcfg.capacity, capacity);
+ stl_p(&blkcfg.seg_max, 128 - 2);
+ stw_p(&blkcfg.cylinders, s->conf->cyls);
+ stl_p(&blkcfg.blk_size, blk_size);
+ stw_p(&blkcfg.min_io_size, s->conf->min_io_size / blk_size);
+ stw_p(&blkcfg.opt_io_size, s->conf->opt_io_size / blk_size);
blkcfg.heads = s->conf->heads;
/*
* We must ensure that the block device capacity is a multiple of
diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h
index 2fb96f8..e5dd447 100644
--- a/hw/display/omap_lcd_template.h
+++ b/hw/display/omap_lcd_template.h
@@ -50,7 +50,7 @@ static void glue(draw_line2_, DEPTH)(void *opaque,
uint8_t v, r, g, b;
do {
- v = ldub_raw((void *) s);
+ v = ldub_p((void *) s);
r = (pal[v & 3] >> 4) & 0xf0;
g = pal[v & 3] & 0xf0;
b = (pal[v & 3] << 4) & 0xf0;
@@ -89,7 +89,7 @@ static void glue(draw_line4_, DEPTH)(void *opaque,
uint8_t v, r, g, b;
do {
- v = ldub_raw((void *) s);
+ v = ldub_p((void *) s);
r = (pal[v & 0xf] >> 4) & 0xf0;
g = pal[v & 0xf] & 0xf0;
b = (pal[v & 0xf] << 4) & 0xf0;
@@ -116,7 +116,7 @@ static void glue(draw_line8_, DEPTH)(void *opaque,
uint8_t v, r, g, b;
do {
- v = ldub_raw((void *) s);
+ v = ldub_p((void *) s);
r = (pal[v] >> 4) & 0xf0;
g = pal[v] & 0xf0;
b = (pal[v] << 4) & 0xf0;
@@ -136,7 +136,7 @@ static void glue(draw_line12_, DEPTH)(void *opaque,
uint8_t r, g, b;
do {
- v = lduw_raw((void *) s);
+ v = lduw_p((void *) s);
r = (v >> 4) & 0xf0;
g = v & 0xf0;
b = (v << 4) & 0xf0;
@@ -159,7 +159,7 @@ static void glue(draw_line16_, DEPTH)(void *opaque,
uint8_t r, g, b;
do {
- v = lduw_raw((void *) s);
+ v = lduw_p((void *) s);
r = (v >> 8) & 0xf8;
g = (v >> 3) & 0xfc;
b = (v << 3) & 0xf8;
diff --git a/hw/display/sm501_template.h b/hw/display/sm501_template.h
index d4cea9e..8c8f092 100644
--- a/hw/display/sm501_template.h
+++ b/hw/display/sm501_template.h
@@ -47,7 +47,7 @@ static void glue(draw_line8_, PIXEL_NAME)(
{
uint8_t v, r, g, b;
do {
- v = ldub_raw(s);
+ v = ldub_p(s);
r = (pal[v] >> 16) & 0xff;
g = (pal[v] >> 8) & 0xff;
b = (pal[v] >> 0) & 0xff;
@@ -64,7 +64,7 @@ static void glue(draw_line16_, PIXEL_NAME)(
uint8_t r, g, b;
do {
- rgb565 = lduw_raw(s);
+ rgb565 = lduw_p(s);
r = ((rgb565 >> 11) & 0x1f) << 3;
g = ((rgb565 >> 5) & 0x3f) << 2;
b = ((rgb565 >> 0) & 0x1f) << 3;
@@ -80,7 +80,7 @@ static void glue(draw_line32_, PIXEL_NAME)(
uint8_t r, g, b;
do {
- ldub_raw(s);
+ ldub_p(s);
#if defined(TARGET_WORDS_BIGENDIAN)
r = s[1];
g = s[2];
diff --git a/hw/display/vga_template.h b/hw/display/vga_template.h
index 6cfae56..90ec9c2 100644
--- a/hw/display/vga_template.h
+++ b/hw/display/vga_template.h
@@ -361,7 +361,7 @@ static void glue(vga_draw_line15_, PIXEL_NAME)(VGACommonState *s1, uint8_t *d,
w = width;
do {
- v = lduw_raw((void *)s);
+ v = lduw_p((void *)s);
r = (v >> 7) & 0xf8;
g = (v >> 2) & 0xf8;
b = (v << 3) & 0xf8;
@@ -386,7 +386,7 @@ static void glue(vga_draw_line16_, PIXEL_NAME)(VGACommonState *s1, uint8_t *d,
w = width;
do {
- v = lduw_raw((void *)s);
+ v = lduw_p((void *)s);
r = (v >> 8) & 0xf8;
g = (v >> 3) & 0xfc;
b = (v << 3) & 0xf8;
diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c
index e1551aa..8f1a16a 100644
--- a/hw/mips/mips_fulong2e.c
+++ b/hw/mips/mips_fulong2e.c
@@ -178,24 +178,24 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_a
/* Small bootloader */
p = (uint32_t *) base;
- stl_raw(p++, 0x0bf00010); /* j 0x1fc00040 */
- stl_raw(p++, 0x00000000); /* nop */
+ stl_p(p++, 0x0bf00010); /* j 0x1fc00040 */
+ stl_p(p++, 0x00000000); /* nop */
/* Second part of the bootloader */
p = (uint32_t *) (base + 0x040);
- stl_raw(p++, 0x3c040000); /* lui a0, 0 */
- stl_raw(p++, 0x34840002); /* ori a0, a0, 2 */
- stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
- stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a0, low(ENVP_ADDR) */
- stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
- stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
- stl_raw(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(env->ram_size) */
- stl_raw(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */
- stl_raw(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff)); /* lui ra, high(kernel_addr) */;
- stl_raw(p++, 0x37ff0000 | (kernel_addr & 0xffff)); /* ori ra, ra, low(kernel_addr) */
- stl_raw(p++, 0x03e00008); /* jr ra */
- stl_raw(p++, 0x00000000); /* nop */
+ stl_p(p++, 0x3c040000); /* lui a0, 0 */
+ stl_p(p++, 0x34840002); /* ori a0, a0, 2 */
+ stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
+ stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a0, low(ENVP_ADDR) */
+ stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
+ stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
+ stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(env->ram_size) */
+ stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */
+ stl_p(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff)); /* lui ra, high(kernel_addr) */;
+ stl_p(p++, 0x37ff0000 | (kernel_addr & 0xffff)); /* ori ra, ra, low(kernel_addr) */
+ stl_p(p++, 0x03e00008); /* jr ra */
+ stl_p(p++, 0x00000000); /* nop */
}
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index ac5ec44..38b3dea 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -609,136 +609,136 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base,
/* Small bootloader */
p = (uint32_t *)base;
- stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */
- stl_raw(p++, 0x00000000); /* nop */
+ stl_p(p++, 0x0bf00160); /* j 0x1fc00580 */
+ stl_p(p++, 0x00000000); /* nop */
/* YAMON service vector */
- stl_raw(base + 0x500, 0xbfc00580); /* start: */
- stl_raw(base + 0x504, 0xbfc0083c); /* print_count: */
- stl_raw(base + 0x520, 0xbfc00580); /* start: */
- stl_raw(base + 0x52c, 0xbfc00800); /* flush_cache: */
- stl_raw(base + 0x534, 0xbfc00808); /* print: */
- stl_raw(base + 0x538, 0xbfc00800); /* reg_cpu_isr: */
- stl_raw(base + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
- stl_raw(base + 0x540, 0xbfc00800); /* reg_ic_isr: */
- stl_raw(base + 0x544, 0xbfc00800); /* unred_ic_isr: */
- stl_raw(base + 0x548, 0xbfc00800); /* reg_esr: */
- stl_raw(base + 0x54c, 0xbfc00800); /* unreg_esr: */
- stl_raw(base + 0x550, 0xbfc00800); /* getchar: */
- stl_raw(base + 0x554, 0xbfc00800); /* syscon_read: */
+ stl_p(base + 0x500, 0xbfc00580); /* start: */
+ stl_p(base + 0x504, 0xbfc0083c); /* print_count: */
+ stl_p(base + 0x520, 0xbfc00580); /* start: */
+ stl_p(base + 0x52c, 0xbfc00800); /* flush_cache: */
+ stl_p(base + 0x534, 0xbfc00808); /* print: */
+ stl_p(base + 0x538, 0xbfc00800); /* reg_cpu_isr: */
+ stl_p(base + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
+ stl_p(base + 0x540, 0xbfc00800); /* reg_ic_isr: */
+ stl_p(base + 0x544, 0xbfc00800); /* unred_ic_isr: */
+ stl_p(base + 0x548, 0xbfc00800); /* reg_esr: */
+ stl_p(base + 0x54c, 0xbfc00800); /* unreg_esr: */
+ stl_p(base + 0x550, 0xbfc00800); /* getchar: */
+ stl_p(base + 0x554, 0xbfc00800); /* syscon_read: */
/* Second part of the bootloader */
p = (uint32_t *) (base + 0x580);
- stl_raw(p++, 0x24040002); /* addiu a0, zero, 2 */
- stl_raw(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
- stl_raw(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
- stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
- stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
- stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
- stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
- stl_raw(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(ram_size) */
- stl_raw(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(ram_size) */
+ stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */
+ stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
+ stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
+ stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
+ stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
+ stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
+ stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
+ stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(ram_size) */
+ stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(ram_size) */
/* Load BAR registers as done by YAMON */
- stl_raw(p++, 0x3c09b400); /* lui t1, 0xb400 */
+ stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
#ifdef TARGET_WORDS_BIGENDIAN
- stl_raw(p++, 0x3c08df00); /* lui t0, 0xdf00 */
+ stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */
#else
- stl_raw(p++, 0x340800df); /* ori t0, r0, 0x00df */
+ stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */
#endif
- stl_raw(p++, 0xad280068); /* sw t0, 0x0068(t1) */
+ stl_p(p++, 0xad280068); /* sw t0, 0x0068(t1) */
- stl_raw(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
+ stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
#ifdef TARGET_WORDS_BIGENDIAN
- stl_raw(p++, 0x3c08c000); /* lui t0, 0xc000 */
+ stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */
#else
- stl_raw(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
+ stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
#endif
- stl_raw(p++, 0xad280048); /* sw t0, 0x0048(t1) */
+ stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */
#ifdef TARGET_WORDS_BIGENDIAN
- stl_raw(p++, 0x3c084000); /* lui t0, 0x4000 */
+ stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */
#else
- stl_raw(p++, 0x34080040); /* ori t0, r0, 0x0040 */
+ stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */
#endif
- stl_raw(p++, 0xad280050); /* sw t0, 0x0050(t1) */
+ stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */
#ifdef TARGET_WORDS_BIGENDIAN
- stl_raw(p++, 0x3c088000); /* lui t0, 0x8000 */
+ stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */
#else
- stl_raw(p++, 0x34080080); /* ori t0, r0, 0x0080 */
+ stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */
#endif
- stl_raw(p++, 0xad280058); /* sw t0, 0x0058(t1) */
+ stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */
#ifdef TARGET_WORDS_BIGENDIAN
- stl_raw(p++, 0x3c083f00); /* lui t0, 0x3f00 */
+ stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */
#else
- stl_raw(p++, 0x3408003f); /* ori t0, r0, 0x003f */
+ stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */
#endif
- stl_raw(p++, 0xad280060); /* sw t0, 0x0060(t1) */
+ stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */
#ifdef TARGET_WORDS_BIGENDIAN
- stl_raw(p++, 0x3c08c100); /* lui t0, 0xc100 */
+ stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */
#else
- stl_raw(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
+ stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
#endif
- stl_raw(p++, 0xad280080); /* sw t0, 0x0080(t1) */
+ stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */
#ifdef TARGET_WORDS_BIGENDIAN
- stl_raw(p++, 0x3c085e00); /* lui t0, 0x5e00 */
+ stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */
#else
- stl_raw(p++, 0x3408005e); /* ori t0, r0, 0x005e */
+ stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */
#endif
- stl_raw(p++, 0xad280088); /* sw t0, 0x0088(t1) */
+ stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */
/* Jump to kernel code */
- stl_raw(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
- stl_raw(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
- stl_raw(p++, 0x03e00008); /* jr ra */
- stl_raw(p++, 0x00000000); /* nop */
+ stl_p(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
+ stl_p(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
+ stl_p(p++, 0x03e00008); /* jr ra */
+ stl_p(p++, 0x00000000); /* nop */
/* YAMON subroutines */
p = (uint32_t *) (base + 0x800);
- stl_raw(p++, 0x03e00008); /* jr ra */
- stl_raw(p++, 0x24020000); /* li v0,0 */
+ stl_p(p++, 0x03e00008); /* jr ra */
+ stl_p(p++, 0x24020000); /* li v0,0 */
/* 808 YAMON print */
- stl_raw(p++, 0x03e06821); /* move t5,ra */
- stl_raw(p++, 0x00805821); /* move t3,a0 */
- stl_raw(p++, 0x00a05021); /* move t2,a1 */
- stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
- stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
- stl_raw(p++, 0x10800005); /* beqz a0,834 */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x0ff0021c); /* jal 870 */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x08000205); /* j 814 */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x01a00008); /* jr t5 */
- stl_raw(p++, 0x01602021); /* move a0,t3 */
+ stl_p(p++, 0x03e06821); /* move t5,ra */
+ stl_p(p++, 0x00805821); /* move t3,a0 */
+ stl_p(p++, 0x00a05021); /* move t2,a1 */
+ stl_p(p++, 0x91440000); /* lbu a0,0(t2) */
+ stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */
+ stl_p(p++, 0x10800005); /* beqz a0,834 */
+ stl_p(p++, 0x00000000); /* nop */
+ stl_p(p++, 0x0ff0021c); /* jal 870 */
+ stl_p(p++, 0x00000000); /* nop */
+ stl_p(p++, 0x08000205); /* j 814 */
+ stl_p(p++, 0x00000000); /* nop */
+ stl_p(p++, 0x01a00008); /* jr t5 */
+ stl_p(p++, 0x01602021); /* move a0,t3 */
/* 0x83c YAMON print_count */
- stl_raw(p++, 0x03e06821); /* move t5,ra */
- stl_raw(p++, 0x00805821); /* move t3,a0 */
- stl_raw(p++, 0x00a05021); /* move t2,a1 */
- stl_raw(p++, 0x00c06021); /* move t4,a2 */
- stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
- stl_raw(p++, 0x0ff0021c); /* jal 870 */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
- stl_raw(p++, 0x258cffff); /* addiu t4,t4,-1 */
- stl_raw(p++, 0x1580fffa); /* bnez t4,84c */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x01a00008); /* jr t5 */
- stl_raw(p++, 0x01602021); /* move a0,t3 */
+ stl_p(p++, 0x03e06821); /* move t5,ra */
+ stl_p(p++, 0x00805821); /* move t3,a0 */
+ stl_p(p++, 0x00a05021); /* move t2,a1 */
+ stl_p(p++, 0x00c06021); /* move t4,a2 */
+ stl_p(p++, 0x91440000); /* lbu a0,0(t2) */
+ stl_p(p++, 0x0ff0021c); /* jal 870 */
+ stl_p(p++, 0x00000000); /* nop */
+ stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */
+ stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */
+ stl_p(p++, 0x1580fffa); /* bnez t4,84c */
+ stl_p(p++, 0x00000000); /* nop */
+ stl_p(p++, 0x01a00008); /* jr t5 */
+ stl_p(p++, 0x01602021); /* move a0,t3 */
/* 0x870 */
- stl_raw(p++, 0x3c08b800); /* lui t0,0xb400 */
- stl_raw(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
- stl_raw(p++, 0x91090005); /* lbu t1,5(t0) */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x31290040); /* andi t1,t1,0x40 */
- stl_raw(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x03e00008); /* jr ra */
- stl_raw(p++, 0xa1040000); /* sb a0,0(t0) */
+ stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */
+ stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
+ stl_p(p++, 0x91090005); /* lbu t1,5(t0) */
+ stl_p(p++, 0x00000000); /* nop */
+ stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */
+ stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
+ stl_p(p++, 0x00000000); /* nop */
+ stl_p(p++, 0x03e00008); /* jr ra */
+ stl_p(p++, 0xa1040000); /* sb a0,0(t0) */
}
diff --git a/hw/scsi/vhost-scsi.c b/hw/scsi/vhost-scsi.c
index 3983a5b..668bafa 100644
--- a/hw/scsi/vhost-scsi.c
+++ b/hw/scsi/vhost-scsi.c
@@ -164,8 +164,8 @@ static void vhost_scsi_set_config(VirtIODevice *vdev,
VirtIOSCSIConfig *scsiconf = (VirtIOSCSIConfig *)config;
VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(vdev);
- if ((uint32_t) ldl_raw(&scsiconf->sense_size) != vs->sense_size ||
- (uint32_t) ldl_raw(&scsiconf->cdb_size) != vs->cdb_size) {
+ if ((uint32_t) ldl_p(&scsiconf->sense_size) != vs->sense_size ||
+ (uint32_t) ldl_p(&scsiconf->cdb_size) != vs->cdb_size) {
error_report("vhost-scsi does not support changing the sense data and CDB sizes");
exit(1);
}
diff --git a/hw/scsi/virtio-scsi.c b/hw/scsi/virtio-scsi.c
index b0d7517..cf9310b 100644
--- a/hw/scsi/virtio-scsi.c
+++ b/hw/scsi/virtio-scsi.c
@@ -416,16 +416,16 @@ static void virtio_scsi_get_config(VirtIODevice *vdev,
VirtIOSCSIConfig *scsiconf = (VirtIOSCSIConfig *)config;
VirtIOSCSICommon *s = VIRTIO_SCSI_COMMON(vdev);
- stl_raw(&scsiconf->num_queues, s->conf.num_queues);
- stl_raw(&scsiconf->seg_max, 128 - 2);
- stl_raw(&scsiconf->max_sectors, s->conf.max_sectors);
- stl_raw(&scsiconf->cmd_per_lun, s->conf.cmd_per_lun);
- stl_raw(&scsiconf->event_info_size, sizeof(VirtIOSCSIEvent));
- stl_raw(&scsiconf->sense_size, s->sense_size);
- stl_raw(&scsiconf->cdb_size, s->cdb_size);
- stw_raw(&scsiconf->max_channel, VIRTIO_SCSI_MAX_CHANNEL);
- stw_raw(&scsiconf->max_target, VIRTIO_SCSI_MAX_TARGET);
- stl_raw(&scsiconf->max_lun, VIRTIO_SCSI_MAX_LUN);
+ stl_p(&scsiconf->num_queues, s->conf.num_queues);
+ stl_p(&scsiconf->seg_max, 128 - 2);
+ stl_p(&scsiconf->max_sectors, s->conf.max_sectors);
+ stl_p(&scsiconf->cmd_per_lun, s->conf.cmd_per_lun);
+ stl_p(&scsiconf->event_info_size, sizeof(VirtIOSCSIEvent));
+ stl_p(&scsiconf->sense_size, s->sense_size);
+ stl_p(&scsiconf->cdb_size, s->cdb_size);
+ stw_p(&scsiconf->max_channel, VIRTIO_SCSI_MAX_CHANNEL);
+ stw_p(&scsiconf->max_target, VIRTIO_SCSI_MAX_TARGET);
+ stl_p(&scsiconf->max_lun, VIRTIO_SCSI_MAX_LUN);
}
static void virtio_scsi_set_config(VirtIODevice *vdev,
@@ -434,14 +434,14 @@ static void virtio_scsi_set_config(VirtIODevice *vdev,
VirtIOSCSIConfig *scsiconf = (VirtIOSCSIConfig *)config;
VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(vdev);
- if ((uint32_t) ldl_raw(&scsiconf->sense_size) >= 65536 ||
- (uint32_t) ldl_raw(&scsiconf->cdb_size) >= 256) {
+ if ((uint32_t) ldl_p(&scsiconf->sense_size) >= 65536 ||
+ (uint32_t) ldl_p(&scsiconf->cdb_size) >= 256) {
error_report("bad data written to virtio-scsi configuration space");
exit(1);
}
- vs->sense_size = ldl_raw(&scsiconf->sense_size);
- vs->cdb_size = ldl_raw(&scsiconf->cdb_size);
+ vs->sense_size = ldl_p(&scsiconf->sense_size);
+ vs->cdb_size = ldl_p(&scsiconf->cdb_size);
}
static uint32_t virtio_scsi_get_features(VirtIODevice *vdev,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Qemu-devel] [RFC PATCH 02/11] softmmu: start introducing SOFTMMU_CODE_ACCESS in softmmu_header.h
2014-05-08 16:09 [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 01/11] hw: use ld_p/st_p instead of ld_raw/st_raw Paolo Bonzini
@ 2014-05-08 16:09 ` Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 03/11] softmmu: move MMUSUFFIX under SOFTMMU_CODE_ACCESS Paolo Bonzini
` (9 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-08 16:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
This preprocessor symbol is already used in softmmu_template.h. We
will use it to distinguish the two "fake" ACCESS_TYPEs
NB_MMU_MODES and NB_MMU_MODES + 1.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
include/exec/exec-all.h | 2 ++
| 8 +++-----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index f9ac332..63713ba 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -342,6 +342,7 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
#define ACCESS_TYPE (NB_MMU_MODES + 1)
#define MEMSUFFIX _code
+#define SOFTMMU_CODE_ACCESS
#define DATA_SIZE 1
#include "exec/softmmu_header.h"
@@ -357,6 +358,7 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
#undef ACCESS_TYPE
#undef MEMSUFFIX
+#undef SOFTMMU_CODE_ACCESS
#endif
--git a/include/exec/softmmu_header.h b/include/exec/softmmu_header.h
index d8d9c81..087b2d4 100644
--- a/include/exec/softmmu_header.h
+++ b/include/exec/softmmu_header.h
@@ -72,7 +72,7 @@
#define RES_TYPE uint32_t
#endif
-#if ACCESS_TYPE == (NB_MMU_MODES + 1)
+#ifdef SOFTMMU_CODE_ACCESS
#define ADDR_READ addr_code
#else
#define ADDR_READ addr_read
@@ -124,7 +124,7 @@ glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
}
#endif
-#if ACCESS_TYPE != (NB_MMU_MODES + 1)
+#ifndef SOFTMMU_CODE_ACCESS
/* generic store macro */
@@ -148,9 +148,7 @@ glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,
}
}
-#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
-#if ACCESS_TYPE != (NB_MMU_MODES + 1)
#if DATA_SIZE == 8
static inline float64 glue(cpu_ldfq, MEMSUFFIX)(CPUArchState *env,
@@ -200,7 +198,7 @@ static inline void glue(cpu_stfl, MEMSUFFIX)(CPUArchState *env,
}
#endif /* DATA_SIZE == 4 */
-#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
+#endif /* !SOFTMMU_CODE_ACCESS */
#undef RES_TYPE
#undef DATA_TYPE
--
1.8.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Qemu-devel] [RFC PATCH 03/11] softmmu: move MMUSUFFIX under SOFTMMU_CODE_ACCESS
2014-05-08 16:09 [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 01/11] hw: use ld_p/st_p instead of ld_raw/st_raw Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 02/11] softmmu: start introducing SOFTMMU_CODE_ACCESS in softmmu_header.h Paolo Bonzini
@ 2014-05-08 16:09 ` Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 04/11] softmmu: move definition of CPU_MMU_INDEX to inclusion site, drop ACCESS_TYPE Paolo Bonzini
` (8 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-08 16:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
| 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
--git a/include/exec/softmmu_header.h b/include/exec/softmmu_header.h
index 087b2d4..cc85a43 100644
--- a/include/exec/softmmu_header.h
+++ b/include/exec/softmmu_header.h
@@ -48,20 +48,11 @@
#endif
#if ACCESS_TYPE < (NB_MMU_MODES)
-
#define CPU_MMU_INDEX ACCESS_TYPE
-#define MMUSUFFIX _mmu
-
#elif ACCESS_TYPE == (NB_MMU_MODES)
-
#define CPU_MMU_INDEX (cpu_mmu_index(env))
-#define MMUSUFFIX _mmu
-
#elif ACCESS_TYPE == (NB_MMU_MODES + 1)
-
#define CPU_MMU_INDEX (cpu_mmu_index(env))
-#define MMUSUFFIX _cmmu
-
#else
#error invalid ACCESS_TYPE
#endif
@@ -74,8 +65,10 @@
#ifdef SOFTMMU_CODE_ACCESS
#define ADDR_READ addr_code
+#define MMUSUFFIX _cmmu
#else
#define ADDR_READ addr_read
+#define MMUSUFFIX _mmu
#endif
/* generic load/store macros */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Qemu-devel] [RFC PATCH 04/11] softmmu: move definition of CPU_MMU_INDEX to inclusion site, drop ACCESS_TYPE
2014-05-08 16:09 [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Paolo Bonzini
` (2 preceding siblings ...)
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 03/11] softmmu: move MMUSUFFIX under SOFTMMU_CODE_ACCESS Paolo Bonzini
@ 2014-05-08 16:09 ` Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 05/11] softmmu: move ALIGNED_ONLY to cpu.h Paolo Bonzini
` (7 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-08 16:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
include/exec/exec-all.h | 4 ++--
include/exec/softmmu_exec.h | 28 ++++++++++++++--------------
| 11 -----------
3 files changed, 16 insertions(+), 27 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 63713ba..3696e9d 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -340,7 +340,7 @@ uint16_t helper_ldw_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
uint32_t helper_ldl_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-#define ACCESS_TYPE (NB_MMU_MODES + 1)
+#define CPU_MMU_INDEX (cpu_mmu_index(env))
#define MEMSUFFIX _code
#define SOFTMMU_CODE_ACCESS
@@ -356,7 +356,7 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
#define DATA_SIZE 8
#include "exec/softmmu_header.h"
-#undef ACCESS_TYPE
+#undef CPU_MMU_INDEX
#undef MEMSUFFIX
#undef SOFTMMU_CODE_ACCESS
diff --git a/include/exec/softmmu_exec.h b/include/exec/softmmu_exec.h
index 470db20..8217733 100644
--- a/include/exec/softmmu_exec.h
+++ b/include/exec/softmmu_exec.h
@@ -22,7 +22,7 @@
/* The memory helpers for tcg-generated code need tcg_target_long etc. */
#include "tcg.h"
-#define ACCESS_TYPE 0
+#define CPU_MMU_INDEX 0
#define MEMSUFFIX MMU_MODE0_SUFFIX
#define DATA_SIZE 1
#include "exec/softmmu_header.h"
@@ -35,10 +35,10 @@
#define DATA_SIZE 8
#include "exec/softmmu_header.h"
-#undef ACCESS_TYPE
+#undef CPU_MMU_INDEX
#undef MEMSUFFIX
-#define ACCESS_TYPE 1
+#define CPU_MMU_INDEX 1
#define MEMSUFFIX MMU_MODE1_SUFFIX
#define DATA_SIZE 1
#include "exec/softmmu_header.h"
@@ -51,12 +51,12 @@
#define DATA_SIZE 8
#include "exec/softmmu_header.h"
-#undef ACCESS_TYPE
+#undef CPU_MMU_INDEX
#undef MEMSUFFIX
#if (NB_MMU_MODES >= 3)
-#define ACCESS_TYPE 2
+#define CPU_MMU_INDEX 2
#define MEMSUFFIX MMU_MODE2_SUFFIX
#define DATA_SIZE 1
#include "exec/softmmu_header.h"
@@ -69,13 +69,13 @@
#define DATA_SIZE 8
#include "exec/softmmu_header.h"
-#undef ACCESS_TYPE
+#undef CPU_MMU_INDEX
#undef MEMSUFFIX
#endif /* (NB_MMU_MODES >= 3) */
#if (NB_MMU_MODES >= 4)
-#define ACCESS_TYPE 3
+#define CPU_MMU_INDEX 3
#define MEMSUFFIX MMU_MODE3_SUFFIX
#define DATA_SIZE 1
#include "exec/softmmu_header.h"
@@ -88,13 +88,13 @@
#define DATA_SIZE 8
#include "exec/softmmu_header.h"
-#undef ACCESS_TYPE
+#undef CPU_MMU_INDEX
#undef MEMSUFFIX
#endif /* (NB_MMU_MODES >= 4) */
#if (NB_MMU_MODES >= 5)
-#define ACCESS_TYPE 4
+#define CPU_MMU_INDEX 4
#define MEMSUFFIX MMU_MODE4_SUFFIX
#define DATA_SIZE 1
#include "exec/softmmu_header.h"
@@ -107,13 +107,13 @@
#define DATA_SIZE 8
#include "exec/softmmu_header.h"
-#undef ACCESS_TYPE
+#undef CPU_MMU_INDEX
#undef MEMSUFFIX
#endif /* (NB_MMU_MODES >= 5) */
#if (NB_MMU_MODES >= 6)
-#define ACCESS_TYPE 5
+#define CPU_MMU_INDEX 5
#define MEMSUFFIX MMU_MODE5_SUFFIX
#define DATA_SIZE 1
#include "exec/softmmu_header.h"
@@ -126,7 +126,7 @@
#define DATA_SIZE 8
#include "exec/softmmu_header.h"
-#undef ACCESS_TYPE
+#undef CPU_MMU_INDEX
#undef MEMSUFFIX
#endif /* (NB_MMU_MODES >= 6) */
@@ -135,7 +135,7 @@
#endif /* (NB_MMU_MODES > 6) */
/* these access are slower, they must be as rare as possible */
-#define ACCESS_TYPE (NB_MMU_MODES)
+#define CPU_MMU_INDEX (cpu_mmu_index(env))
#define MEMSUFFIX _data
#define DATA_SIZE 1
#include "exec/softmmu_header.h"
@@ -148,7 +148,7 @@
#define DATA_SIZE 8
#include "exec/softmmu_header.h"
-#undef ACCESS_TYPE
+#undef CPU_MMU_INDEX
#undef MEMSUFFIX
#define ldub(p) ldub_data(p)
--git a/include/exec/softmmu_header.h b/include/exec/softmmu_header.h
index cc85a43..bb18f97 100644
--- a/include/exec/softmmu_header.h
+++ b/include/exec/softmmu_header.h
@@ -47,16 +47,6 @@
#error unsupported data size
#endif
-#if ACCESS_TYPE < (NB_MMU_MODES)
-#define CPU_MMU_INDEX ACCESS_TYPE
-#elif ACCESS_TYPE == (NB_MMU_MODES)
-#define CPU_MMU_INDEX (cpu_mmu_index(env))
-#elif ACCESS_TYPE == (NB_MMU_MODES + 1)
-#define CPU_MMU_INDEX (cpu_mmu_index(env))
-#else
-#error invalid ACCESS_TYPE
-#endif
-
#if DATA_SIZE == 8
#define RES_TYPE uint64_t
#else
@@ -199,6 +189,5 @@ static inline void glue(cpu_stfl, MEMSUFFIX)(CPUArchState *env,
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
-#undef CPU_MMU_INDEX
#undef MMUSUFFIX
#undef ADDR_READ
--
1.8.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Qemu-devel] [RFC PATCH 05/11] softmmu: move ALIGNED_ONLY to cpu.h
2014-05-08 16:09 [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Paolo Bonzini
` (3 preceding siblings ...)
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 04/11] softmmu: move definition of CPU_MMU_INDEX to inclusion site, drop ACCESS_TYPE Paolo Bonzini
@ 2014-05-08 16:09 ` Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 06/11] softmmu: commonize helper definitions Paolo Bonzini
` (6 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-08 16:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Prepare for moving softmmu_header.h inclusion out of .c files
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target-alpha/cpu.h | 1 +
target-alpha/mem_helper.c | 1 -
target-mips/cpu.h | 1 +
target-mips/op_helper.c | 1 -
target-sparc/cpu.h | 2 ++
target-sparc/ldst_helper.c | 1 -
target-xtensa/cpu.h | 1 +
target-xtensa/op_helper.c | 1 -
8 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 07d9f63..d9b861f 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -24,6 +24,7 @@
#include "qemu-common.h"
#define TARGET_LONG_BITS 64
+#define ALIGNED_ONLY
#define CPUArchState struct CPUAlphaState
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 5964bdc..fa9e8a3 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -134,7 +134,6 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
#include "exec/softmmu_exec.h"
#define MMUSUFFIX _mmu
-#define ALIGNED_ONLY
#define SHIFT 0
#include "exec/softmmu_template.h"
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 6c2014e..a9b2c7a 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -3,6 +3,7 @@
//#define DEBUG_OP
+#define ALIGNED_ONLY
#define TARGET_HAS_ICE 1
#define ELF_MACHINE EM_MIPS
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 4edec6c..209dcdf 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2133,7 +2133,6 @@ static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
int is_user, uintptr_t retaddr);
#define MMUSUFFIX _mmu
-#define ALIGNED_ONLY
#define SHIFT 0
#include "exec/softmmu_template.h"
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index f72451d..836f87f 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -5,6 +5,8 @@
#include "qemu-common.h"
#include "qemu/bswap.h"
+#define ALIGNED_ONLY
+
#if !defined(TARGET_SPARC64)
#define TARGET_LONG_BITS 32
#define TARGET_DPREGS 16
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index ec14802..d676f16 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -70,7 +70,6 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
int is_user, uintptr_t retaddr);
#include "exec/softmmu_exec.h"
#define MMUSUFFIX _mmu
-#define ALIGNED_ONLY
#define SHIFT 0
#include "exec/softmmu_template.h"
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index e210bac..d797d26 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -28,6 +28,7 @@
#ifndef CPU_XTENSA_H
#define CPU_XTENSA_H
+#define ALIGNED_ONLY
#define TARGET_LONG_BITS 32
#define ELF_MACHINE EM_XTENSA
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index b531019..a2439be 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -34,7 +34,6 @@
static void do_unaligned_access(CPUXtensaState *env,
target_ulong addr, int is_write, int is_user, uintptr_t retaddr);
-#define ALIGNED_ONLY
#define MMUSUFFIX _mmu
#define SHIFT 0
--
1.8.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Qemu-devel] [RFC PATCH 06/11] softmmu: commonize helper definitions
2014-05-08 16:09 [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Paolo Bonzini
` (4 preceding siblings ...)
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 05/11] softmmu: move ALIGNED_ONLY to cpu.h Paolo Bonzini
@ 2014-05-08 16:09 ` Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 07/11] softmmu: move softmmu_template.h out of include/ Paolo Bonzini
` (5 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-08 16:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
They do not need to be in op_helper.c. Because cputlb.c now includes
softmmu_template.h twice for each size, io_readX must be elided the
second time through.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
cputlb.c | 18 ++++++++++++++++--
include/exec/softmmu_template.h | 2 ++
target-alpha/mem_helper.c | 14 --------------
target-arm/op_helper.c | 14 --------------
target-cris/op_helper.c | 14 --------------
target-i386/mem_helper.c | 18 ------------------
target-lm32/op_helper.c | 10 ----------
target-m68k/op_helper.c | 14 --------------
target-microblaze/op_helper.c | 10 ----------
target-mips/op_helper.c | 14 --------------
target-moxie/helper.c | 14 --------------
target-openrisc/mmu_helper.c | 13 -------------
target-ppc/mmu_helper.c | 14 --------------
target-s390x/mem_helper.c | 14 --------------
target-sh4/op_helper.c | 14 --------------
target-sparc/ldst_helper.c | 13 -------------
target-unicore32/op_helper.c | 14 --------------
target-xtensa/op_helper.c | 14 --------------
18 files changed, 18 insertions(+), 220 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 214c945..0a884f8 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -27,6 +27,7 @@
#include "exec/memory-internal.h"
#include "exec/ram_addr.h"
+#include "tcg/tcg.h"
//#define DEBUG_TLB
//#define DEBUG_TLB_CHECK
@@ -330,6 +331,21 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
return qemu_ram_addr_from_host_nofail(p);
}
+#define MMUSUFFIX _mmu
+
+#define SHIFT 0
+#include "exec/softmmu_template.h"
+
+#define SHIFT 1
+#include "exec/softmmu_template.h"
+
+#define SHIFT 2
+#include "exec/softmmu_template.h"
+
+#define SHIFT 3
+#include "exec/softmmu_template.h"
+#undef MMUSUFFIX
+
#define MMUSUFFIX _cmmu
#undef GETPC_ADJ
#define GETPC_ADJ 0
@@ -348,5 +364,3 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
#define SHIFT 3
#include "exec/softmmu_template.h"
-
-#undef env
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index 73ed7cf..ed8725d 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -116,6 +116,7 @@
# define helper_te_st_name helper_le_st_name
#endif
+#ifndef SOFTMMU_CODE_ACCESS
static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
hwaddr physaddr,
target_ulong addr,
@@ -135,6 +136,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
io_mem_read(mr, physaddr, &val, 1 << SHIFT);
return val;
}
+#endif
#ifdef SOFTMMU_CODE_ACCESS
static __attribute__((unused))
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index fa9e8a3..5a94f3e 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -133,20 +133,6 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
#include "exec/softmmu_exec.h"
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
/* try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index fb90676..2e46381 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -58,20 +58,6 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
#include "exec/softmmu_exec.h"
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
/* try to fill the TLB and return an exception if error. If retaddr is
* NULL, it means that the function was called in C code (i.e. not
* from generated code or from helper.c)
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index bd9a583..86e3a2d 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -37,20 +37,6 @@
#if !defined(CONFIG_USER_ONLY)
#include "exec/softmmu_exec.h"
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
index b3b811b..b32cb08 100644
--- a/target-i386/mem_helper.c
+++ b/target-i386/mem_helper.c
@@ -110,24 +110,6 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v)
}
#if !defined(CONFIG_USER_ONLY)
-
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
-#endif
-
-#if !defined(CONFIG_USER_ONLY)
/* try to fill the TLB and return an exception if error. If retaddr is
* NULL, it means that the function was called in C code (i.e. not
* from generated code or from helper.c)
diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
index 2f36b7b..16180dc 100644
--- a/target-lm32/op_helper.c
+++ b/target-lm32/op_helper.c
@@ -13,16 +13,6 @@
#endif
#if !defined(CONFIG_USER_ONLY)
-#define MMUSUFFIX _mmu
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
void raise_exception(CPULM32State *env, int index)
{
CPUState *cs = CPU(lm32_env_get_cpu(env));
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 06302b1..291a3af 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -36,20 +36,6 @@ extern int semihosting_enabled;
#include "exec/softmmu_exec.h"
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index f8fb7f9..24f24ab 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -28,16 +28,6 @@
#if !defined(CONFIG_USER_ONLY)
#include "exec/softmmu_exec.h"
-#define MMUSUFFIX _mmu
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
/* Try to fill the TLB and return an exception if error. If retaddr is
* NULL, it means that the function was called in C code (i.e. not
* from generated code or from helper.c)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 209dcdf..b0e8165 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2132,20 +2132,6 @@ static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
target_ulong addr, int is_write,
int is_user, uintptr_t retaddr);
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
int is_write, int is_user, uintptr_t retaddr)
{
diff --git a/target-moxie/helper.c b/target-moxie/helper.c
index 3d0c34d..9daaee8 100644
--- a/target-moxie/helper.c
+++ b/target-moxie/helper.c
@@ -29,20 +29,6 @@
#include "qemu/host-utils.h"
#include "helper.h"
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c
index fb457c7..5263634 100644
--- a/target-openrisc/mmu_helper.c
+++ b/target-openrisc/mmu_helper.c
@@ -22,19 +22,6 @@
#ifndef CONFIG_USER_ONLY
#include "exec/softmmu_exec.h"
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 1771863..90c0de3 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -2905,20 +2905,6 @@ void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type)
#include "exec/softmmu_exec.h"
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
/* try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index d8ca300..d0b353e 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -26,20 +26,6 @@
#if !defined(CONFIG_USER_ONLY)
#include "exec/softmmu_exec.h"
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
/* try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 720a97b..ee386ce 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -24,20 +24,6 @@
#ifndef CONFIG_USER_ONLY
#include "exec/softmmu_exec.h"
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index d676f16..2d6ea70 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -69,19 +69,6 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
target_ulong addr, int is_write,
int is_user, uintptr_t retaddr);
#include "exec/softmmu_exec.h"
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
#endif
#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index 4c6950d..2a8c9d9 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -243,20 +243,6 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i)
#ifndef CONFIG_USER_ONLY
#include "exec/softmmu_exec.h"
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
{
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index a2439be..f421c18 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -34,20 +34,6 @@
static void do_unaligned_access(CPUXtensaState *env,
target_ulong addr, int is_write, int is_user, uintptr_t retaddr);
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
static void do_unaligned_access(CPUXtensaState *env,
target_ulong addr, int is_write, int is_user, uintptr_t retaddr)
{
--
1.8.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Qemu-devel] [RFC PATCH 07/11] softmmu: move softmmu_template.h out of include/
2014-05-08 16:09 [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Paolo Bonzini
` (5 preceding siblings ...)
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 06/11] softmmu: commonize helper definitions Paolo Bonzini
@ 2014-05-08 16:09 ` Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 08/11] softmmu: make do_unaligned_access extern Paolo Bonzini
` (4 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-08 16:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
It is only included in cputlb.c now.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
cputlb.c | 16 ++++++++--------
include/exec/softmmu_template.h => softmmu_template.h | 0
2 files changed, 8 insertions(+), 8 deletions(-)
rename include/exec/softmmu_template.h => softmmu_template.h (100%)
diff --git a/cputlb.c b/cputlb.c
index 0a884f8..e70cf7a 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -334,16 +334,16 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
#define MMUSUFFIX _mmu
#define SHIFT 0
-#include "exec/softmmu_template.h"
+#include "softmmu_template.h"
#define SHIFT 1
-#include "exec/softmmu_template.h"
+#include "softmmu_template.h"
#define SHIFT 2
-#include "exec/softmmu_template.h"
+#include "softmmu_template.h"
#define SHIFT 3
-#include "exec/softmmu_template.h"
+#include "softmmu_template.h"
#undef MMUSUFFIX
#define MMUSUFFIX _cmmu
@@ -354,13 +354,13 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
#define SOFTMMU_CODE_ACCESS
#define SHIFT 0
-#include "exec/softmmu_template.h"
+#include "softmmu_template.h"
#define SHIFT 1
-#include "exec/softmmu_template.h"
+#include "softmmu_template.h"
#define SHIFT 2
-#include "exec/softmmu_template.h"
+#include "softmmu_template.h"
#define SHIFT 3
-#include "exec/softmmu_template.h"
+#include "softmmu_template.h"
diff --git a/include/exec/softmmu_template.h b/softmmu_template.h
similarity index 100%
rename from include/exec/softmmu_template.h
rename to softmmu_template.h
--
1.8.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Qemu-devel] [RFC PATCH 08/11] softmmu: make do_unaligned_access extern
2014-05-08 16:09 [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Paolo Bonzini
` (6 preceding siblings ...)
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 07/11] softmmu: move softmmu_template.h out of include/ Paolo Bonzini
@ 2014-05-08 16:09 ` Paolo Bonzini
2014-05-13 6:53 ` Andreas Färber
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 09/11] target-arm: move arm_*_code to a separate file Paolo Bonzini
` (3 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-08 16:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
We will reference it from more files in the next patch.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target-alpha/cpu.h | 3 +++
target-alpha/mem_helper.c | 4 ++--
target-mips/cpu.h | 3 +++
target-mips/op_helper.c | 8 ++------
target-sparc/cpu.h | 4 ++++
target-sparc/ldst_helper.c | 9 +++------
target-xtensa/cpu.h | 3 +++
target-xtensa/op_helper.c | 5 +----
8 files changed, 21 insertions(+), 18 deletions(-)
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index d9b861f..242068f 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -498,6 +498,9 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
*pflags = flags;
}
+void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
+ int is_write, int is_user, uintptr_t retaddr);
+
#include "exec/exec-all.h"
#endif /* !defined (__CPU_ALPHA_H__) */
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 5a94f3e..1e80167 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -96,8 +96,8 @@ uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
return ret;
}
-static void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
- int is_write, int is_user, uintptr_t retaddr)
+void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
+ int is_write, int is_user, uintptr_t retaddr)
{
AlphaCPU *cpu = alpha_env_get_cpu(env);
CPUState *cs = CPU(cpu);
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index a9b2c7a..29d3d8f 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -782,4 +782,7 @@ static inline void compute_hflags(CPUMIPSState *env)
}
}
+void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
+ int is_write, int is_user, uintptr_t retaddr);
+
#endif /* !defined (__MIPS_CPU_H__) */
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index b0e8165..aebd1e4 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2128,12 +2128,8 @@ void helper_wait(CPUMIPSState *env)
#if !defined(CONFIG_USER_ONLY)
-static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
- target_ulong addr, int is_write,
- int is_user, uintptr_t retaddr);
-
-static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
- int is_write, int is_user, uintptr_t retaddr)
+void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
+ int is_write, int is_user, uintptr_t retaddr)
{
env->CP0_BadVAddr = addr;
do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 836f87f..aaedf43 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -751,6 +751,10 @@ static inline bool tb_am_enabled(int tb_flags)
#endif
}
+void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
+ target_ulong addr, int is_write,
+ int is_user, uintptr_t retaddr);
+
#include "exec/exec-all.h"
#endif
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 2d6ea70..2bc9b3a 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -65,9 +65,6 @@
#define QT1 (env->qt1)
#if !defined(CONFIG_USER_ONLY)
-static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
- target_ulong addr, int is_write,
- int is_user, uintptr_t retaddr);
#include "exec/softmmu_exec.h"
#endif
@@ -2411,9 +2408,9 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
#endif
#if !defined(CONFIG_USER_ONLY)
-static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
- target_ulong addr, int is_write,
- int is_user, uintptr_t retaddr)
+void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
+ target_ulong addr, int is_write,
+ int is_user, uintptr_t retaddr)
{
SPARCCPU *cpu = sparc_env_get_cpu(env);
#ifdef DEBUG_UNALIGNED
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index d797d26..ecb7ae6 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -523,6 +523,9 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
}
}
+void do_unaligned_access(CPUXtensaState *env,
+ target_ulong addr, int is_write, int is_user, uintptr_t retaddr);
+
#include "exec/cpu-all.h"
#include "exec/exec-all.h"
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index f421c18..4a174a3 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -31,10 +31,7 @@
#include "exec/softmmu_exec.h"
#include "exec/address-spaces.h"
-static void do_unaligned_access(CPUXtensaState *env,
- target_ulong addr, int is_write, int is_user, uintptr_t retaddr);
-
-static void do_unaligned_access(CPUXtensaState *env,
+void do_unaligned_access(CPUXtensaState *env,
target_ulong addr, int is_write, int is_user, uintptr_t retaddr)
{
XtensaCPU *cpu = xtensa_env_get_cpu(env);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Qemu-devel] [RFC PATCH 09/11] target-arm: move arm_*_code to a separate file
2014-05-08 16:09 [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Paolo Bonzini
` (7 preceding siblings ...)
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 08/11] softmmu: make do_unaligned_access extern Paolo Bonzini
@ 2014-05-08 16:09 ` Paolo Bonzini
2014-05-13 7:03 ` Andreas Färber
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 10/11] softmmu: introduce cpu_ldst.h Paolo Bonzini
` (2 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-08 16:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
These will soon require cpu_ldst.h, so move them out of cpu.h.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target-arm/arm_ldst.h | 47 ++++++++++++++++++++++++++++++++++++++++++++++
target-arm/cpu.h | 22 ----------------------
target-arm/helper.c | 1 +
target-arm/translate-a64.c | 1 +
target-arm/translate.c | 1 +
5 files changed, 50 insertions(+), 22 deletions(-)
create mode 100644 target-arm/arm_ldst.h
diff --git a/target-arm/arm_ldst.h b/target-arm/arm_ldst.h
new file mode 100644
index 0000000..42260ac
--- /dev/null
+++ b/target-arm/arm_ldst.h
@@ -0,0 +1,47 @@
+/*
+ * ARM load/store instructions for code (armeb-user support)
+ *
+ * Copyright (c) 2012 CodeSourcery, LLC
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef ARM_LDST_H
+#define ARM_LDST_H
+
+#include "qemu/bswap.h"
+
+/* Load an instruction and return it in the standard little-endian order */
+static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
+ bool do_swap)
+{
+ uint32_t insn = cpu_ldl_code(env, addr);
+ if (do_swap) {
+ return bswap32(insn);
+ }
+ return insn;
+}
+
+/* Ditto, for a halfword (Thumb) instruction */
+static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
+ bool do_swap)
+{
+ uint16_t insn = cpu_lduw_code(env, addr);
+ if (do_swap) {
+ return bswap16(insn);
+ }
+ return insn;
+}
+
+#endif
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c83f249..b4ee31b 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1195,26 +1195,4 @@ static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
}
}
-/* Load an instruction and return it in the standard little-endian order */
-static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
- bool do_swap)
-{
- uint32_t insn = cpu_ldl_code(env, addr);
- if (do_swap) {
- return bswap32(insn);
- }
- return insn;
-}
-
-/* Ditto, for a halfword (Thumb) instruction */
-static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
- bool do_swap)
-{
- uint16_t insn = cpu_lduw_code(env, addr);
- if (do_swap) {
- return bswap16(insn);
- }
- return insn;
-}
-
#endif
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3be917c..8b19bdc 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -7,6 +7,7 @@
#include "sysemu/sysemu.h"
#include "qemu/bitops.h"
#include "qemu/crc32c.h"
+#include "arm_ldst.h"
#include <zlib.h> /* For crc32 */
#ifndef CONFIG_USER_ONLY
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index b62db4d..fc09a36 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -25,6 +25,7 @@
#include "cpu.h"
#include "tcg-op.h"
#include "qemu/log.h"
+#include "arm_ldst.h"
#include "translate.h"
#include "internals.h"
#include "qemu/host-utils.h"
diff --git a/target-arm/translate.c b/target-arm/translate.c
index a4d920b..6916f9f 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -30,6 +30,7 @@
#include "tcg-op.h"
#include "qemu/log.h"
#include "qemu/bitops.h"
+#include "arm_ldst.h"
#include "helper.h"
#define GEN_HELPER 1
--
1.8.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Qemu-devel] [RFC PATCH 10/11] softmmu: introduce cpu_ldst.h
2014-05-08 16:09 [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Paolo Bonzini
` (8 preceding siblings ...)
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 09/11] target-arm: move arm_*_code to a separate file Paolo Bonzini
@ 2014-05-08 16:09 ` Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 11/11] softmmu: move all load/store functions to cpu_ldst.h Paolo Bonzini
2014-05-12 17:37 ` [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Richard Henderson
11 siblings, 0 replies; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-08 16:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
This will collect all load and store helpers soon. For now
it is just a replacement for softmmu_exec.h, which this patch
stops including directly, but we also include it where this will
be necessary in order to simplify the next patch.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
bsd-user/qemu.h | 1 +
cputlb.c | 1 +
include/exec/cpu_ldst.h | 35 +++++++++++++++++++++++++++++++++++
linux-user/qemu.h | 1 +
monitor.c | 1 +
target-alpha/mem_helper.c | 4 +---
target-alpha/translate.c | 1 +
target-arm/arm_ldst.h | 1 +
target-arm/op_helper.c | 3 +--
target-cris/helper.c | 1 +
target-cris/op_helper.c | 3 +--
target-cris/translate.c | 1 +
target-i386/fpu_helper.c | 5 +----
target-i386/mem_helper.c | 5 +----
target-i386/misc_helper.c | 5 +----
target-i386/seg_helper.c | 5 +----
target-i386/svm_helper.c | 5 +----
target-i386/translate.c | 1 +
target-lm32/op_helper.c | 2 +-
target-lm32/translate.c | 1 +
target-m68k/op_helper.c | 3 +--
target-m68k/translate.c | 1 +
target-microblaze/op_helper.c | 2 +-
target-microblaze/translate.c | 1 +
target-mips/op_helper.c | 5 +----
target-mips/translate.c | 1 +
target-moxie/helper.c | 2 +-
target-moxie/translate.c | 1 +
target-openrisc/mmu_helper.c | 2 +-
target-openrisc/translate.c | 1 +
target-ppc/excp_helper.c | 1 +
target-ppc/mem_helper.c | 5 +----
target-ppc/mmu_helper.c | 3 +--
target-ppc/translate.c | 1 +
target-s390x/fpu_helper.c | 5 +----
target-s390x/helper.c | 1 +
target-s390x/mem_helper.c | 2 +-
target-s390x/misc_helper.c | 2 +-
target-s390x/translate.c | 1 +
target-sh4/op_helper.c | 2 +-
target-sh4/translate.c | 1 +
target-sparc/ldst_helper.c | 5 +----
target-sparc/translate.c | 1 +
target-unicore32/op_helper.c | 3 +--
target-unicore32/translate.c | 1 +
target-xtensa/op_helper.c | 3 ++-
target-xtensa/translate.c | 1 +
tci.c | 1 +
user-exec.c | 1 +
49 files changed, 84 insertions(+), 57 deletions(-)
create mode 100644 include/exec/cpu_ldst.h
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index ddc74ed..9d90668 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -5,6 +5,7 @@
#include <string.h>
#include "cpu.h"
+#include "exec/cpu_ldst.h"
#undef DEBUG_REMAP
#ifdef DEBUG_REMAP
diff --git a/cputlb.c b/cputlb.c
index e70cf7a..afd3705 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -22,6 +22,7 @@
#include "exec/exec-all.h"
#include "exec/memory.h"
#include "exec/address-spaces.h"
+#include "exec/cpu_ldst.h"
#include "exec/cputlb.h"
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
new file mode 100644
index 0000000..a6b7884
--- /dev/null
+++ b/include/exec/cpu_ldst.h
@@ -0,0 +1,35 @@
+/*
+ * Software MMU support
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+/*
+ * Generate inline load/store functions for all MMU modes (typically
+ * at least _user and _kernel) as well as _data versions, for all data
+ * sizes.
+ *
+ * Used by target op helpers.
+ *
+ * MMU mode suffixes are defined in target cpu.h.
+ */
+#ifndef CPU_LDST_H
+#define CPU_LDST_H
+
+#if !defined(CONFIG_USER_ONLY)
+#include "exec/softmmu_exec.h"
+#endif
+
+#endif /* CPU_LDST_H */
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index 36d4a73..ba3d8ab 100644
--- a/linux-user/qemu.h
+++ b/linux-user/qemu.h
@@ -5,6 +5,7 @@
#include <string.h>
#include "cpu.h"
+#include "exec/cpu_ldst.h"
#undef DEBUG_REMAP
#ifdef DEBUG_REMAP
diff --git a/monitor.c b/monitor.c
index 1266ba0..067ce48 100644
--- a/monitor.c
+++ b/monitor.c
@@ -66,6 +66,7 @@
#include "trace/simple.h"
#endif
#include "exec/memory.h"
+#include "exec/cpu_ldst.h"
#include "qmp-commands.h"
#include "hmp.h"
#include "qemu/thread.h"
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 1e80167..e261988 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -19,7 +19,7 @@
#include "cpu.h"
#include "helper.h"
-
+#include "exec/cpu_ldst.h"
/* Softmmu support */
#ifndef CONFIG_USER_ONLY
@@ -131,8 +131,6 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
dynamic_excp(env, 0, EXCP_MCHK, 0);
}
-#include "exec/softmmu_exec.h"
-
/* try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index d0357ff..d1b2680 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -21,6 +21,7 @@
#include "disas/disas.h"
#include "qemu/host-utils.h"
#include "tcg-op.h"
+#include "exec/cpu_ldst.h"
#include "helper.h"
#define GEN_HELPER 1
diff --git a/target-arm/arm_ldst.h b/target-arm/arm_ldst.h
index 42260ac..233d8a0 100644
--- a/target-arm/arm_ldst.h
+++ b/target-arm/arm_ldst.h
@@ -20,6 +20,7 @@
#ifndef ARM_LDST_H
#define ARM_LDST_H
+#include "exec/cpu_ldst.h"
#include "qemu/bswap.h"
/* Load an instruction and return it in the standard little-endian order */
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 2e46381..5d5747b 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -19,6 +19,7 @@
#include "cpu.h"
#include "helper.h"
#include "internals.h"
+#include "exec/cpu_ldst.h"
#define SIGNBIT (uint32_t)0x80000000
#define SIGNBIT64 ((uint64_t)1 << 63)
@@ -56,8 +57,6 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
-
/* try to fill the TLB and return an exception if error. If retaddr is
* NULL, it means that the function was called in C code (i.e. not
* from generated code or from helper.c)
diff --git a/target-cris/helper.c b/target-cris/helper.c
index 4092d27..e8b8261 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "mmu.h"
#include "qemu/host-utils.h"
+#include "exec/cpu_ldst.h"
//#define CRIS_HELPER_DEBUG
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index 86e3a2d..1331e97 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -22,6 +22,7 @@
#include "mmu.h"
#include "helper.h"
#include "qemu/host-utils.h"
+#include "exec/cpu_ldst.h"
//#define CRIS_OP_HELPER_DEBUG
@@ -35,8 +36,6 @@
#endif
#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
-
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 724f920..c358f89 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -28,6 +28,7 @@
#include "tcg-op.h"
#include "helper.h"
#include "mmu.h"
+#include "exec/cpu_ldst.h"
#include "crisv32-decode.h"
#define GEN_HELPER 1
diff --git a/target-i386/fpu_helper.c b/target-i386/fpu_helper.c
index de7ba76..f280691 100644
--- a/target-i386/fpu_helper.c
+++ b/target-i386/fpu_helper.c
@@ -22,10 +22,7 @@
#include "helper.h"
#include "qemu/aes.h"
#include "qemu/host-utils.h"
-
-#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
-#endif /* !defined(CONFIG_USER_ONLY) */
+#include "exec/cpu_ldst.h"
#define FPU_RC_MASK 0xc00
#define FPU_RC_NEAR 0x000
diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
index b32cb08..7ff3e0b 100644
--- a/target-i386/mem_helper.c
+++ b/target-i386/mem_helper.c
@@ -19,10 +19,7 @@
#include "cpu.h"
#include "helper.h"
-
-#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
-#endif /* !defined(CONFIG_USER_ONLY) */
+#include "exec/cpu_ldst.h"
/* broken thread support */
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
index 1e2da1e..07fa5c7 100644
--- a/target-i386/misc_helper.c
+++ b/target-i386/misc_helper.c
@@ -20,10 +20,7 @@
#include "cpu.h"
#include "exec/ioport.h"
#include "helper.h"
-
-#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
-#endif /* !defined(CONFIG_USER_ONLY) */
+#include "exec/cpu_ldst.h"
/* check if Port I/O is allowed in TSS */
static inline void check_io(CPUX86State *env, int addr, int size)
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index 8c3f92c..75e5c17 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -21,13 +21,10 @@
#include "cpu.h"
#include "qemu/log.h"
#include "helper.h"
+#include "exec/cpu_ldst.h"
//#define DEBUG_PCALL
-#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
-#endif /* !defined(CONFIG_USER_ONLY) */
-
#ifdef DEBUG_PCALL
# define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__)
# define LOG_PCALL_STATE(cpu) \
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index aa17ecd..5ca792b 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -20,10 +20,7 @@
#include "cpu.h"
#include "exec/cpu-all.h"
#include "helper.h"
-
-#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
-#endif /* !defined(CONFIG_USER_ONLY) */
+#include "exec/cpu_ldst.h"
/* Secure Virtual Machine helpers */
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 02625e3..1d20ba2 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -27,6 +27,7 @@
#include "cpu.h"
#include "disas/disas.h"
#include "tcg-op.h"
+#include "exec/cpu_ldst.h"
#include "helper.h"
#define GEN_HELPER 1
diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
index 16180dc..9bfa593 100644
--- a/target-lm32/op_helper.c
+++ b/target-lm32/op_helper.c
@@ -6,7 +6,7 @@
#include "hw/lm32/lm32_pic.h"
#include "hw/char/lm32_juart.h"
-#include "exec/softmmu_exec.h"
+#include "exec/cpu_ldst.h"
#ifndef CONFIG_USER_ONLY
#include "sysemu/sysemu.h"
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index c8abd1f..2f542a8 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -22,6 +22,7 @@
#include "helper.h"
#include "tcg-op.h"
+#include "exec/cpu_ldst.h"
#include "hw/lm32/lm32_pic.h"
#define GEN_HELPER 1
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 291a3af..bf4d872 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -18,6 +18,7 @@
*/
#include "cpu.h"
#include "helper.h"
+#include "exec/cpu_ldst.h"
#if defined(CONFIG_USER_ONLY)
@@ -34,8 +35,6 @@ void do_interrupt_m68k_hardirq(CPUM68KState *env)
extern int semihosting_enabled;
-#include "exec/softmmu_exec.h"
-
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index cd66289..cb89ec7 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -22,6 +22,7 @@
#include "disas/disas.h"
#include "tcg-op.h"
#include "qemu/log.h"
+#include "exec/cpu_ldst.h"
#include "helper.h"
#define GEN_HELPER 1
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 24f24ab..ec05728 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -22,11 +22,11 @@
#include "cpu.h"
#include "helper.h"
#include "qemu/host-utils.h"
+#include "exec/cpu_ldst.h"
#define D(x)
#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
/* Try to fill the TLB and return an exception if error. If retaddr is
* NULL, it means that the function was called in C code (i.e. not
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 782a489..cd9a5a9 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -23,6 +23,7 @@
#include "tcg-op.h"
#include "helper.h"
#include "microblaze-decode.h"
+#include "exec/cpu_ldst.h"
#define GEN_HELPER 1
#include "helper.h"
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index aebd1e4..4e71b32 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -21,10 +21,7 @@
#include "qemu/host-utils.h"
#include "helper.h"
-
-#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
-#endif /* !defined(CONFIG_USER_ONLY) */
+#include "exec/cpu_ldst.h"
#ifndef CONFIG_USER_ONLY
static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 05f82d2..a95e824 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -24,6 +24,7 @@
#include "cpu.h"
#include "disas/disas.h"
#include "tcg-op.h"
+#include "exec/cpu_ldst.h"
#include "helper.h"
#define GEN_HELPER 1
diff --git a/target-moxie/helper.c b/target-moxie/helper.c
index 9daaee8..cef4858 100644
--- a/target-moxie/helper.c
+++ b/target-moxie/helper.c
@@ -25,7 +25,7 @@
#include "cpu.h"
#include "mmu.h"
#include "exec/exec-all.h"
-#include "exec/softmmu_exec.h"
+#include "exec/cpu_ldst.h"
#include "qemu/host-utils.h"
#include "helper.h"
diff --git a/target-moxie/translate.c b/target-moxie/translate.c
index 63f889f..d8c9780 100644
--- a/target-moxie/translate.c
+++ b/target-moxie/translate.c
@@ -32,6 +32,7 @@
#include "exec/exec-all.h"
#include "disas/disas.h"
#include "tcg-op.h"
+#include "exec/cpu_ldst.h"
#include "helper.h"
#define GEN_HELPER 1
diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c
index 5263634..ee1c6f6 100644
--- a/target-openrisc/mmu_helper.c
+++ b/target-openrisc/mmu_helper.c
@@ -19,9 +19,9 @@
*/
#include "cpu.h"
+#include "exec/cpu_ldst.h"
#ifndef CONFIG_USER_ONLY
-#include "exec/softmmu_exec.h"
void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 852b5e6..27a35e7 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -26,6 +26,7 @@
#include "qemu/log.h"
#include "config.h"
#include "qemu/bitops.h"
+#include "exec/cpu_ldst.h"
#include "helper.h"
#define GEN_HELPER 1
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 4fa297d..c93ae68 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -18,6 +18,7 @@
*/
#include "cpu.h"
#include "helper.h"
+#include "exec/cpu_ldst.h"
#include "helper_regs.h"
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index f35ed03..c170b64 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -21,10 +21,7 @@
#include "helper.h"
#include "helper_regs.h"
-
-#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
-#endif /* !defined(CONFIG_USER_ONLY) */
+#include "exec/cpu_ldst.h"
//#define DEBUG_OP
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 90c0de3..5452b68 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -22,6 +22,7 @@
#include "kvm_ppc.h"
#include "mmu-hash64.h"
#include "mmu-hash32.h"
+#include "exec/cpu_ldst.h"
//#define DEBUG_MMU
//#define DEBUG_BATS
@@ -2903,8 +2904,6 @@ void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type)
/*****************************************************************************/
-#include "exec/softmmu_exec.h"
-
/* try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e3fcb03..48a1c48 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -22,6 +22,7 @@
#include "disas/disas.h"
#include "tcg-op.h"
#include "qemu/host-utils.h"
+#include "exec/cpu_ldst.h"
#include "helper.h"
#define GEN_HELPER 1
diff --git a/target-s390x/fpu_helper.c b/target-s390x/fpu_helper.c
index 3e9c7b2..02fd233 100644
--- a/target-s390x/fpu_helper.c
+++ b/target-s390x/fpu_helper.c
@@ -20,10 +20,7 @@
#include "cpu.h"
#include "helper.h"
-
-#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
-#endif
+#include "exec/cpu_ldst.h"
/* #define DEBUG_HELPER */
#ifdef DEBUG_HELPER
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index aa628b8..ef6d127 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "exec/gdbstub.h"
#include "qemu/timer.h"
+#include "exec/cpu_ldst.h"
#ifndef CONFIG_USER_ONLY
#include "sysemu/sysemu.h"
#endif
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index d0b353e..adfaf6e 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -20,11 +20,11 @@
#include "cpu.h"
#include "helper.h"
+#include "exec/cpu_ldst.h"
/*****************************************************************************/
/* Softmmu support */
#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
/* try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
index cdbbb79..10460c6 100644
--- a/target-s390x/misc_helper.c
+++ b/target-s390x/misc_helper.c
@@ -28,9 +28,9 @@
#ifdef CONFIG_KVM
#include <linux/kvm.h>
#endif
+#include "exec/cpu_ldst.h"
#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
#include "sysemu/cpus.h"
#include "sysemu/sysemu.h"
#include "hw/s390x/ebcdic.h"
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 81b7e33..00a1a36 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -33,6 +33,7 @@
#include "tcg-op.h"
#include "qemu/log.h"
#include "qemu/host-utils.h"
+#include "exec/cpu_ldst.h"
/* global register indexes */
static TCGv_ptr cpu_env;
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index ee386ce..2b476fd 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -20,9 +20,9 @@
#include <stdlib.h>
#include "cpu.h"
#include "helper.h"
+#include "exec/cpu_ldst.h"
#ifndef CONFIG_USER_ONLY
-#include "exec/softmmu_exec.h"
void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 2360609..464ac81 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -23,6 +23,7 @@
#include "cpu.h"
#include "disas/disas.h"
#include "tcg-op.h"
+#include "exec/cpu_ldst.h"
#include "helper.h"
#define GEN_HELPER 1
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 2bc9b3a..96f2d8a 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -19,6 +19,7 @@
#include "cpu.h"
#include "helper.h"
+#include "exec/cpu_ldst.h"
//#define DEBUG_MMU
//#define DEBUG_MXCC
@@ -64,10 +65,6 @@
#define QT0 (env->qt0)
#define QT1 (env->qt1)
-#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
-#endif
-
#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
/* Calculates TSB pointer value for fault page size 8k or 64k */
static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 2de1c4a..b3c73fb 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -28,6 +28,7 @@
#include "disas/disas.h"
#include "helper.h"
#include "tcg-op.h"
+#include "exec/cpu_ldst.h"
#define GEN_HELPER 1
#include "helper.h"
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index 2a8c9d9..7e65871 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -10,6 +10,7 @@
*/
#include "cpu.h"
#include "helper.h"
+#include "exec/cpu_ldst.h"
#define SIGNBIT (uint32_t)0x80000000
#define SIGNBIT64 ((uint64_t)1 << 63)
@@ -241,8 +242,6 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i)
}
#ifndef CONFIG_USER_ONLY
-#include "exec/softmmu_exec.h"
-
void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
{
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index c2402cf..cffd040 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -18,6 +18,7 @@
#include "disas/disas.h"
#include "tcg-op.h"
#include "qemu/log.h"
+#include "exec/cpu_ldst.h"
#include "helper.h"
#define GEN_HELPER 1
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 4a174a3..3593185 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -28,8 +28,9 @@
#include "cpu.h"
#include "helper.h"
#include "qemu/host-utils.h"
-#include "exec/softmmu_exec.h"
+#include "exec/cpu_ldst.h"
#include "exec/address-spaces.h"
+#include "qemu/timer.h"
void do_unaligned_access(CPUXtensaState *env,
target_ulong addr, int is_write, int is_user, uintptr_t retaddr)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 764cee9..6eee696 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -36,6 +36,7 @@
#include "tcg-op.h"
#include "qemu/log.h"
#include "sysemu/sysemu.h"
+#include "exec/cpu_ldst.h"
#include "helper.h"
#define GEN_HELPER 1
diff --git a/tci.c b/tci.c
index 6523ab8..0acf1a1 100644
--- a/tci.c
+++ b/tci.c
@@ -26,6 +26,7 @@
#include "qemu-common.h"
#include "exec/exec-all.h" /* MAX_OPC_PARAM_IARGS */
+#include "exec/cpu_ldst.h"
#include "tcg-op.h"
/* Marker for missing code. */
diff --git a/user-exec.c b/user-exec.c
index 8ed6fec..1ff8673 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -21,6 +21,7 @@
#include "disas/disas.h"
#include "tcg.h"
#include "qemu/bitops.h"
+#include "exec/cpu_ldst.h"
#undef EAX
#undef ECX
--
1.8.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Qemu-devel] [RFC PATCH 11/11] softmmu: move all load/store functions to cpu_ldst.h
2014-05-08 16:09 [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Paolo Bonzini
` (9 preceding siblings ...)
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 10/11] softmmu: introduce cpu_ldst.h Paolo Bonzini
@ 2014-05-08 16:09 ` Paolo Bonzini
2014-05-12 17:36 ` Richard Henderson
2014-05-13 7:13 ` Andreas Färber
2014-05-12 17:37 ` [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Richard Henderson
11 siblings, 2 replies; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-08 16:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Unify pieces of cpu-all.h, exec-all.h, softmmu_exec.h and tcg/tcg.h
into a single new header file with all helpers.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
include/exec/cpu-all.h | 119 -------
include/exec/cpu_ldst.h | 369 ++++++++++++++++++++-
.../exec/{softmmu_header.h => cpu_ldst_template.h} | 2 +-
include/exec/exec-all.h | 25 --
include/exec/softmmu_exec.h | 216 ------------
tcg/tcg.h | 13 -
6 files changed, 368 insertions(+), 376 deletions(-)
rename include/exec/{softmmu_header.h => cpu_ldst_template.h} (98%)
delete mode 100644 include/exec/softmmu_exec.h
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index fb649a4..e1e8290 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -198,127 +198,8 @@ extern unsigned long reserved_va;
#define RESERVED_VA 0ul
#endif
-/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
-#define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))
-
-#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
-#define h2g_valid(x) 1
-#else
-#define h2g_valid(x) ({ \
- unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
- (__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
- (!RESERVED_VA || (__guest < RESERVED_VA)); \
-})
#endif
-#define h2g_nocheck(x) ({ \
- unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
- (abi_ulong)__ret; \
-})
-
-#define h2g(x) ({ \
- /* Check if given address fits target address space */ \
- assert(h2g_valid(x)); \
- h2g_nocheck(x); \
-})
-
-#define saddr(x) g2h(x)
-#define laddr(x) g2h(x)
-
-#else /* !CONFIG_USER_ONLY */
-/* NOTE: we use double casts if pointers and target_ulong have
- different sizes */
-#define saddr(x) (uint8_t *)(intptr_t)(x)
-#define laddr(x) (uint8_t *)(intptr_t)(x)
-#endif
-
-#define ldub_raw(p) ldub_p(laddr((p)))
-#define ldsb_raw(p) ldsb_p(laddr((p)))
-#define lduw_raw(p) lduw_p(laddr((p)))
-#define ldsw_raw(p) ldsw_p(laddr((p)))
-#define ldl_raw(p) ldl_p(laddr((p)))
-#define ldq_raw(p) ldq_p(laddr((p)))
-#define ldfl_raw(p) ldfl_p(laddr((p)))
-#define ldfq_raw(p) ldfq_p(laddr((p)))
-#define stb_raw(p, v) stb_p(saddr((p)), v)
-#define stw_raw(p, v) stw_p(saddr((p)), v)
-#define stl_raw(p, v) stl_p(saddr((p)), v)
-#define stq_raw(p, v) stq_p(saddr((p)), v)
-#define stfl_raw(p, v) stfl_p(saddr((p)), v)
-#define stfq_raw(p, v) stfq_p(saddr((p)), v)
-
-
-#if defined(CONFIG_USER_ONLY)
-
-/* if user mode, no other memory access functions */
-#define ldub(p) ldub_raw(p)
-#define ldsb(p) ldsb_raw(p)
-#define lduw(p) lduw_raw(p)
-#define ldsw(p) ldsw_raw(p)
-#define ldl(p) ldl_raw(p)
-#define ldq(p) ldq_raw(p)
-#define ldfl(p) ldfl_raw(p)
-#define ldfq(p) ldfq_raw(p)
-#define stb(p, v) stb_raw(p, v)
-#define stw(p, v) stw_raw(p, v)
-#define stl(p, v) stl_raw(p, v)
-#define stq(p, v) stq_raw(p, v)
-#define stfl(p, v) stfl_raw(p, v)
-#define stfq(p, v) stfq_raw(p, v)
-
-#define cpu_ldub_code(env1, p) ldub_raw(p)
-#define cpu_ldsb_code(env1, p) ldsb_raw(p)
-#define cpu_lduw_code(env1, p) lduw_raw(p)
-#define cpu_ldsw_code(env1, p) ldsw_raw(p)
-#define cpu_ldl_code(env1, p) ldl_raw(p)
-#define cpu_ldq_code(env1, p) ldq_raw(p)
-
-#define cpu_ldub_data(env, addr) ldub_raw(addr)
-#define cpu_lduw_data(env, addr) lduw_raw(addr)
-#define cpu_ldsw_data(env, addr) ldsw_raw(addr)
-#define cpu_ldl_data(env, addr) ldl_raw(addr)
-#define cpu_ldq_data(env, addr) ldq_raw(addr)
-
-#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
-#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
-#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
-#define cpu_stq_data(env, addr, data) stq_raw(addr, data)
-
-#define cpu_ldub_kernel(env, addr) ldub_raw(addr)
-#define cpu_lduw_kernel(env, addr) lduw_raw(addr)
-#define cpu_ldsw_kernel(env, addr) ldsw_raw(addr)
-#define cpu_ldl_kernel(env, addr) ldl_raw(addr)
-#define cpu_ldq_kernel(env, addr) ldq_raw(addr)
-
-#define cpu_stb_kernel(env, addr, data) stb_raw(addr, data)
-#define cpu_stw_kernel(env, addr, data) stw_raw(addr, data)
-#define cpu_stl_kernel(env, addr, data) stl_raw(addr, data)
-#define cpu_stq_kernel(env, addr, data) stq_raw(addr, data)
-
-#define ldub_kernel(p) ldub_raw(p)
-#define ldsb_kernel(p) ldsb_raw(p)
-#define lduw_kernel(p) lduw_raw(p)
-#define ldsw_kernel(p) ldsw_raw(p)
-#define ldl_kernel(p) ldl_raw(p)
-#define ldq_kernel(p) ldq_raw(p)
-#define ldfl_kernel(p) ldfl_raw(p)
-#define ldfq_kernel(p) ldfq_raw(p)
-#define stb_kernel(p, v) stb_raw(p, v)
-#define stw_kernel(p, v) stw_raw(p, v)
-#define stl_kernel(p, v) stl_raw(p, v)
-#define stq_kernel(p, v) stq_raw(p, v)
-#define stfl_kernel(p, v) stfl_raw(p, v)
-#define stfq_kernel(p, vt) stfq_raw(p, v)
-
-#define cpu_ldub_data(env, addr) ldub_raw(addr)
-#define cpu_lduw_data(env, addr) lduw_raw(addr)
-#define cpu_ldl_data(env, addr) ldl_raw(addr)
-
-#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
-#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
-#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
-#endif /* defined(CONFIG_USER_ONLY) */
-
/* page related stuff */
#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index a6b7884..e5550e7 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -28,8 +28,373 @@
#ifndef CPU_LDST_H
#define CPU_LDST_H
-#if !defined(CONFIG_USER_ONLY)
-#include "exec/softmmu_exec.h"
+#if defined(CONFIG_USER_ONLY)
+/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
+#define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))
+
+#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
+#define h2g_valid(x) 1
+#else
+#define h2g_valid(x) ({ \
+ unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
+ (__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
+ (!RESERVED_VA || (__guest < RESERVED_VA)); \
+})
+#endif
+
+#define h2g_nocheck(x) ({ \
+ unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
+ (abi_ulong)__ret; \
+})
+
+#define h2g(x) ({ \
+ /* Check if given address fits target address space */ \
+ assert(h2g_valid(x)); \
+ h2g_nocheck(x); \
+})
+
+#define saddr(x) g2h(x)
+#define laddr(x) g2h(x)
+
+#else /* !CONFIG_USER_ONLY */
+/* NOTE: we use double casts if pointers and target_ulong have
+ different sizes */
+#define saddr(x) (uint8_t *)(intptr_t)(x)
+#define laddr(x) (uint8_t *)(intptr_t)(x)
#endif
+#define ldub_raw(p) ldub_p(laddr((p)))
+#define ldsb_raw(p) ldsb_p(laddr((p)))
+#define lduw_raw(p) lduw_p(laddr((p)))
+#define ldsw_raw(p) ldsw_p(laddr((p)))
+#define ldl_raw(p) ldl_p(laddr((p)))
+#define ldq_raw(p) ldq_p(laddr((p)))
+#define ldfl_raw(p) ldfl_p(laddr((p)))
+#define ldfq_raw(p) ldfq_p(laddr((p)))
+#define stb_raw(p, v) stb_p(saddr((p)), v)
+#define stw_raw(p, v) stw_p(saddr((p)), v)
+#define stl_raw(p, v) stl_p(saddr((p)), v)
+#define stq_raw(p, v) stq_p(saddr((p)), v)
+#define stfl_raw(p, v) stfl_p(saddr((p)), v)
+#define stfq_raw(p, v) stfq_p(saddr((p)), v)
+
+
+#if defined(CONFIG_USER_ONLY)
+
+/* if user mode, no other memory access functions */
+#define ldub(p) ldub_raw(p)
+#define ldsb(p) ldsb_raw(p)
+#define lduw(p) lduw_raw(p)
+#define ldsw(p) ldsw_raw(p)
+#define ldl(p) ldl_raw(p)
+#define ldq(p) ldq_raw(p)
+#define ldfl(p) ldfl_raw(p)
+#define ldfq(p) ldfq_raw(p)
+#define stb(p, v) stb_raw(p, v)
+#define stw(p, v) stw_raw(p, v)
+#define stl(p, v) stl_raw(p, v)
+#define stq(p, v) stq_raw(p, v)
+#define stfl(p, v) stfl_raw(p, v)
+#define stfq(p, v) stfq_raw(p, v)
+
+#define cpu_ldub_code(env1, p) ldub_raw(p)
+#define cpu_ldsb_code(env1, p) ldsb_raw(p)
+#define cpu_lduw_code(env1, p) lduw_raw(p)
+#define cpu_ldsw_code(env1, p) ldsw_raw(p)
+#define cpu_ldl_code(env1, p) ldl_raw(p)
+#define cpu_ldq_code(env1, p) ldq_raw(p)
+
+#define cpu_ldub_data(env, addr) ldub_raw(addr)
+#define cpu_lduw_data(env, addr) lduw_raw(addr)
+#define cpu_ldsw_data(env, addr) ldsw_raw(addr)
+#define cpu_ldl_data(env, addr) ldl_raw(addr)
+#define cpu_ldq_data(env, addr) ldq_raw(addr)
+
+#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
+#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
+#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
+#define cpu_stq_data(env, addr, data) stq_raw(addr, data)
+
+#define cpu_ldub_kernel(env, addr) ldub_raw(addr)
+#define cpu_lduw_kernel(env, addr) lduw_raw(addr)
+#define cpu_ldsw_kernel(env, addr) ldsw_raw(addr)
+#define cpu_ldl_kernel(env, addr) ldl_raw(addr)
+#define cpu_ldq_kernel(env, addr) ldq_raw(addr)
+
+#define cpu_stb_kernel(env, addr, data) stb_raw(addr, data)
+#define cpu_stw_kernel(env, addr, data) stw_raw(addr, data)
+#define cpu_stl_kernel(env, addr, data) stl_raw(addr, data)
+#define cpu_stq_kernel(env, addr, data) stq_raw(addr, data)
+
+#define ldub_kernel(p) ldub_raw(p)
+#define ldsb_kernel(p) ldsb_raw(p)
+#define lduw_kernel(p) lduw_raw(p)
+#define ldsw_kernel(p) ldsw_raw(p)
+#define ldl_kernel(p) ldl_raw(p)
+#define ldq_kernel(p) ldq_raw(p)
+#define ldfl_kernel(p) ldfl_raw(p)
+#define ldfq_kernel(p) ldfq_raw(p)
+#define stb_kernel(p, v) stb_raw(p, v)
+#define stw_kernel(p, v) stw_raw(p, v)
+#define stl_kernel(p, v) stl_raw(p, v)
+#define stq_kernel(p, v) stq_raw(p, v)
+#define stfl_kernel(p, v) stfl_raw(p, v)
+#define stfq_kernel(p, vt) stfq_raw(p, v)
+
+#define cpu_ldub_data(env, addr) ldub_raw(addr)
+#define cpu_lduw_data(env, addr) lduw_raw(addr)
+#define cpu_ldl_data(env, addr) ldl_raw(addr)
+
+#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
+#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
+#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
+
+#else
+
+/* XXX: find something cleaner.
+ * Furthermore, this is false for 64 bits targets
+ */
+#define ldul_user ldl_user
+#define ldul_kernel ldl_kernel
+#define ldul_hypv ldl_hypv
+#define ldul_executive ldl_executive
+#define ldul_supervisor ldl_supervisor
+
+/* The memory helpers for tcg-generated code need tcg_target_long etc. */
+#include "tcg.h"
+
+uint8_t helper_ldb_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
+uint16_t helper_ldw_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
+uint32_t helper_ldl_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
+uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
+
+void helper_stb_mmu(CPUArchState *env, target_ulong addr,
+ uint8_t val, int mmu_idx);
+void helper_stw_mmu(CPUArchState *env, target_ulong addr,
+ uint16_t val, int mmu_idx);
+void helper_stl_mmu(CPUArchState *env, target_ulong addr,
+ uint32_t val, int mmu_idx);
+void helper_stq_mmu(CPUArchState *env, target_ulong addr,
+ uint64_t val, int mmu_idx);
+
+uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
+uint16_t helper_ldw_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
+uint32_t helper_ldl_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
+uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
+
+#define CPU_MMU_INDEX 0
+#define MEMSUFFIX MMU_MODE0_SUFFIX
+#define DATA_SIZE 1
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 2
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 4
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 8
+#include "exec/cpu_ldst_template.h"
+#undef CPU_MMU_INDEX
+#undef MEMSUFFIX
+
+#define CPU_MMU_INDEX 1
+#define MEMSUFFIX MMU_MODE1_SUFFIX
+#define DATA_SIZE 1
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 2
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 4
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 8
+#include "exec/cpu_ldst_template.h"
+#undef CPU_MMU_INDEX
+#undef MEMSUFFIX
+
+#if (NB_MMU_MODES >= 3)
+
+#define CPU_MMU_INDEX 2
+#define MEMSUFFIX MMU_MODE2_SUFFIX
+#define DATA_SIZE 1
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 2
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 4
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 8
+#include "exec/cpu_ldst_template.h"
+#undef CPU_MMU_INDEX
+#undef MEMSUFFIX
+#endif /* (NB_MMU_MODES >= 3) */
+
+#if (NB_MMU_MODES >= 4)
+
+#define CPU_MMU_INDEX 3
+#define MEMSUFFIX MMU_MODE3_SUFFIX
+#define DATA_SIZE 1
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 2
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 4
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 8
+#include "exec/cpu_ldst_template.h"
+#undef CPU_MMU_INDEX
+#undef MEMSUFFIX
+#endif /* (NB_MMU_MODES >= 4) */
+
+#if (NB_MMU_MODES >= 5)
+
+#define CPU_MMU_INDEX 4
+#define MEMSUFFIX MMU_MODE4_SUFFIX
+#define DATA_SIZE 1
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 2
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 4
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 8
+#include "exec/cpu_ldst_template.h"
+#undef CPU_MMU_INDEX
+#undef MEMSUFFIX
+#endif /* (NB_MMU_MODES >= 5) */
+
+#if (NB_MMU_MODES >= 6)
+
+#define CPU_MMU_INDEX 5
+#define MEMSUFFIX MMU_MODE5_SUFFIX
+#define DATA_SIZE 1
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 2
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 4
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 8
+#include "exec/cpu_ldst_template.h"
+#undef CPU_MMU_INDEX
+#undef MEMSUFFIX
+#endif /* (NB_MMU_MODES >= 6) */
+
+#if (NB_MMU_MODES > 6)
+#error "NB_MMU_MODES > 6 is not supported for now"
+#endif /* (NB_MMU_MODES > 6) */
+
+/* these access are slower, they must be as rare as possible */
+#define CPU_MMU_INDEX (cpu_mmu_index(env))
+#define MEMSUFFIX _data
+#define DATA_SIZE 1
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 2
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 4
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 8
+#include "exec/cpu_ldst_template.h"
+#undef CPU_MMU_INDEX
+#undef MEMSUFFIX
+
+#define ldub(p) ldub_data(p)
+#define ldsb(p) ldsb_data(p)
+#define lduw(p) lduw_data(p)
+#define ldsw(p) ldsw_data(p)
+#define ldl(p) ldl_data(p)
+#define ldq(p) ldq_data(p)
+
+#define stb(p, v) stb_data(p, v)
+#define stw(p, v) stw_data(p, v)
+#define stl(p, v) stl_data(p, v)
+#define stq(p, v) stq_data(p, v)
+
+#define CPU_MMU_INDEX (cpu_mmu_index(env))
+#define MEMSUFFIX _code
+#define SOFTMMU_CODE_ACCESS
+
+#define DATA_SIZE 1
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 2
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 4
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 8
+#include "exec/cpu_ldst_template.h"
+
+#undef CPU_MMU_INDEX
+#undef MEMSUFFIX
+#undef SOFTMMU_CODE_ACCESS
+
+/**
+ * tlb_vaddr_to_host:
+ * @env: CPUArchState
+ * @addr: guest virtual address to look up
+ * @access_type: 0 for read, 1 for write, 2 for execute
+ * @mmu_idx: MMU index to use for lookup
+ *
+ * Look up the specified guest virtual index in the TCG softmmu TLB.
+ * If the TLB contains a host virtual address suitable for direct RAM
+ * access, then return it. Otherwise (TLB miss, TLB entry is for an
+ * I/O access, etc) return NULL.
+ *
+ * This is the equivalent of the initial fast-path code used by
+ * TCG backends for guest load and store accesses.
+ */
+static inline void *tlb_vaddr_to_host(CPUArchState *env, target_ulong addr,
+ int access_type, int mmu_idx)
+{
+ int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
+ CPUTLBEntry *tlbentry = &env->tlb_table[mmu_idx][index];
+ target_ulong tlb_addr;
+ uintptr_t haddr;
+
+ switch (access_type) {
+ case 0:
+ tlb_addr = tlbentry->addr_read;
+ break;
+ case 1:
+ tlb_addr = tlbentry->addr_write;
+ break;
+ case 2:
+ tlb_addr = tlbentry->addr_code;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if ((addr & TARGET_PAGE_MASK)
+ != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
+ /* TLB entry is for a different page */
+ return NULL;
+ }
+
+ if (tlb_addr & ~TARGET_PAGE_MASK) {
+ /* IO access */
+ return NULL;
+ }
+
+ haddr = addr + env->tlb_table[mmu_idx][index].addend;
+ return (void *)haddr;
+}
+
+#endif /* defined(CONFIG_USER_ONLY) */
+
#endif /* CPU_LDST_H */
diff --git a/include/exec/softmmu_header.h b/include/exec/cpu_ldst_template.h
similarity index 98%
rename from include/exec/softmmu_header.h
rename to include/exec/cpu_ldst_template.h
index bb18f97..006093a 100644
--- a/include/exec/softmmu_header.h
+++ b/include/exec/cpu_ldst_template.h
@@ -8,7 +8,7 @@
* 32 and 64 bit cases, also generate floating point functions with
* the same size.
*
- * Not used directly but included from softmmu_exec.h and exec-all.h.
+ * Not used directly but included from cpu_ldst.h.
*
* Copyright (c) 2003 Fabrice Bellard
*
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 3696e9d..b93e2c9 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -335,31 +335,6 @@ bool io_mem_write(struct MemoryRegion *mr, hwaddr addr,
void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr);
-uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-uint16_t helper_ldw_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-uint32_t helper_ldl_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-
-#define CPU_MMU_INDEX (cpu_mmu_index(env))
-#define MEMSUFFIX _code
-#define SOFTMMU_CODE_ACCESS
-
-#define DATA_SIZE 1
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 2
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 4
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 8
-#include "exec/softmmu_header.h"
-
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#undef SOFTMMU_CODE_ACCESS
-
#endif
#if defined(CONFIG_USER_ONLY)
diff --git a/include/exec/softmmu_exec.h b/include/exec/softmmu_exec.h
deleted file mode 100644
index 8217733..0000000
--- a/include/exec/softmmu_exec.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * Software MMU support
- *
- * Generate inline load/store functions for all MMU modes (typically
- * at least _user and _kernel) as well as _data versions, for all data
- * sizes.
- *
- * Used by target op helpers.
- *
- * MMU mode suffixes are defined in target cpu.h.
- */
-
-/* XXX: find something cleaner.
- * Furthermore, this is false for 64 bits targets
- */
-#define ldul_user ldl_user
-#define ldul_kernel ldl_kernel
-#define ldul_hypv ldl_hypv
-#define ldul_executive ldl_executive
-#define ldul_supervisor ldl_supervisor
-
-/* The memory helpers for tcg-generated code need tcg_target_long etc. */
-#include "tcg.h"
-
-#define CPU_MMU_INDEX 0
-#define MEMSUFFIX MMU_MODE0_SUFFIX
-#define DATA_SIZE 1
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 2
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 4
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 8
-#include "exec/softmmu_header.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-
-#define CPU_MMU_INDEX 1
-#define MEMSUFFIX MMU_MODE1_SUFFIX
-#define DATA_SIZE 1
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 2
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 4
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 8
-#include "exec/softmmu_header.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-
-#if (NB_MMU_MODES >= 3)
-
-#define CPU_MMU_INDEX 2
-#define MEMSUFFIX MMU_MODE2_SUFFIX
-#define DATA_SIZE 1
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 2
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 4
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 8
-#include "exec/softmmu_header.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 3) */
-
-#if (NB_MMU_MODES >= 4)
-
-#define CPU_MMU_INDEX 3
-#define MEMSUFFIX MMU_MODE3_SUFFIX
-#define DATA_SIZE 1
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 2
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 4
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 8
-#include "exec/softmmu_header.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 4) */
-
-#if (NB_MMU_MODES >= 5)
-
-#define CPU_MMU_INDEX 4
-#define MEMSUFFIX MMU_MODE4_SUFFIX
-#define DATA_SIZE 1
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 2
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 4
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 8
-#include "exec/softmmu_header.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 5) */
-
-#if (NB_MMU_MODES >= 6)
-
-#define CPU_MMU_INDEX 5
-#define MEMSUFFIX MMU_MODE5_SUFFIX
-#define DATA_SIZE 1
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 2
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 4
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 8
-#include "exec/softmmu_header.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 6) */
-
-#if (NB_MMU_MODES > 6)
-#error "NB_MMU_MODES > 6 is not supported for now"
-#endif /* (NB_MMU_MODES > 6) */
-
-/* these access are slower, they must be as rare as possible */
-#define CPU_MMU_INDEX (cpu_mmu_index(env))
-#define MEMSUFFIX _data
-#define DATA_SIZE 1
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 2
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 4
-#include "exec/softmmu_header.h"
-
-#define DATA_SIZE 8
-#include "exec/softmmu_header.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-
-#define ldub(p) ldub_data(p)
-#define ldsb(p) ldsb_data(p)
-#define lduw(p) lduw_data(p)
-#define ldsw(p) ldsw_data(p)
-#define ldl(p) ldl_data(p)
-#define ldq(p) ldq_data(p)
-
-#define stb(p, v) stb_data(p, v)
-#define stw(p, v) stw_data(p, v)
-#define stl(p, v) stl_data(p, v)
-#define stq(p, v) stq_data(p, v)
-
-/**
- * tlb_vaddr_to_host:
- * @env: CPUArchState
- * @addr: guest virtual address to look up
- * @access_type: 0 for read, 1 for write, 2 for execute
- * @mmu_idx: MMU index to use for lookup
- *
- * Look up the specified guest virtual index in the TCG softmmu TLB.
- * If the TLB contains a host virtual address suitable for direct RAM
- * access, then return it. Otherwise (TLB miss, TLB entry is for an
- * I/O access, etc) return NULL.
- *
- * This is the equivalent of the initial fast-path code used by
- * TCG backends for guest load and store accesses.
- */
-static inline void *tlb_vaddr_to_host(CPUArchState *env, target_ulong addr,
- int access_type, int mmu_idx)
-{
- int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
- CPUTLBEntry *tlbentry = &env->tlb_table[mmu_idx][index];
- target_ulong tlb_addr;
- uintptr_t haddr;
-
- switch (access_type) {
- case 0:
- tlb_addr = tlbentry->addr_read;
- break;
- case 1:
- tlb_addr = tlbentry->addr_write;
- break;
- case 2:
- tlb_addr = tlbentry->addr_code;
- break;
- default:
- g_assert_not_reached();
- }
-
- if ((addr & TARGET_PAGE_MASK)
- != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
- /* TLB entry is for a different page */
- return NULL;
- }
-
- if (tlb_addr & ~TARGET_PAGE_MASK) {
- /* IO access */
- return NULL;
- }
-
- haddr = addr + env->tlb_table[mmu_idx][index].addend;
- return (void *)haddr;
-}
diff --git a/tcg/tcg.h b/tcg/tcg.h
index a6a2d06..8090d45 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -846,19 +846,6 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
# define helper_ret_stq_mmu helper_le_stq_mmu
#endif
-uint8_t helper_ldb_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-uint16_t helper_ldw_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-uint32_t helper_ldl_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-
-void helper_stb_mmu(CPUArchState *env, target_ulong addr,
- uint8_t val, int mmu_idx);
-void helper_stw_mmu(CPUArchState *env, target_ulong addr,
- uint16_t val, int mmu_idx);
-void helper_stl_mmu(CPUArchState *env, target_ulong addr,
- uint32_t val, int mmu_idx);
-void helper_stq_mmu(CPUArchState *env, target_ulong addr,
- uint64_t val, int mmu_idx);
#endif /* CONFIG_SOFTMMU */
#endif /* TCG_H */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [RFC PATCH 01/11] hw: use ld_p/st_p instead of ld_raw/st_raw
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 01/11] hw: use ld_p/st_p instead of ld_raw/st_raw Paolo Bonzini
@ 2014-05-09 18:18 ` Peter Maydell
2014-05-09 19:03 ` Paolo Bonzini
0 siblings, 1 reply; 22+ messages in thread
From: Peter Maydell @ 2014-05-09 18:18 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: QEMU Developers, Richard Henderson
On 8 May 2014 17:09, Paolo Bonzini <pbonzini@redhat.com> wrote:
> The ld_raw and st_raw definitions are only needed in code that
> must compile for both user-mode and softmmu emulation. Device
> models can use the equivalent ld_p/st_p which are simple
> pointer accessors.
>
> The checkpatch situation of nseries.c and mips_malta.c is
> messy. I'm only doing a textual substitution in this RFC,
> maintainers should let me know what they prefer.
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> hw/9pfs/virtio-9p-device.c | 2 +-
> hw/arm/nseries.c | 236 ++++++++++++++++++++---------------------
> hw/block/virtio-blk.c | 12 +--
> hw/display/omap_lcd_template.h | 10 +-
> hw/display/sm501_template.h | 6 +-
> hw/display/vga_template.h | 4 +-
> hw/mips/mips_fulong2e.c | 28 ++---
> hw/mips/mips_malta.c | 176 +++++++++++++++---------------
> hw/scsi/vhost-scsi.c | 4 +-
> hw/scsi/virtio-scsi.c | 28 ++---
The virtio parts of this look dubious. What actual
endianness does the virtio spec say that things like the
block device geometry should have in memory? I suspect
we should be using the use-the-virtio-endianness accessors
Greg's on-list patches implement, which renders the
raw-vs-p question moot. In any case you'll probably
have patch conflicts there.
For nseries.c I think I'd prefer we do the checkpatch fixups.
There's no reason we can't do this now (ie we don't wait
on the fixes which make the rest of this series an RFC),
so if you want to make this patch smaller you could submit
a patch for the ARM bits of this and I'll take it in
target-arm.next. (Or I can do it, if you'd rather.)
I suspect the OMAP display device at least should technically
be doing lduw_le_p(), since this isn't the CPU doing the
access, but an independent peripheral doing DMA reads
from memory. It's kind of an academic question for the
moment since you'll only see an OMAP device in an
LE-target QEMU binary, though, so straight substitution
is reasonable.
thanks
-- PMM
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [RFC PATCH 01/11] hw: use ld_p/st_p instead of ld_raw/st_raw
2014-05-09 18:18 ` Peter Maydell
@ 2014-05-09 19:03 ` Paolo Bonzini
0 siblings, 0 replies; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-09 19:03 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, Richard Henderson
Il 09/05/2014 20:18, Peter Maydell ha scritto:
> The virtio parts of this look dubious. What actual
> endianness does the virtio spec say that things like the
> block device geometry should have in memory? I suspect
> we should be using the use-the-virtio-endianness accessors
> Greg's on-list patches implement, which renders the
> raw-vs-p question moot. In any case you'll probably
> have patch conflicts there.
It's "target" endianness. Yes, there would be conflicts.
> For nseries.c I think I'd prefer we do the checkpatch fixups.
> There's no reason we can't do this now (ie we don't wait
> on the fixes which make the rest of this series an RFC),
Ok.
Paolo
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [RFC PATCH 11/11] softmmu: move all load/store functions to cpu_ldst.h
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 11/11] softmmu: move all load/store functions to cpu_ldst.h Paolo Bonzini
@ 2014-05-12 17:36 ` Richard Henderson
2014-05-13 7:13 ` Andreas Färber
1 sibling, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2014-05-12 17:36 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel; +Cc: peter.maydell
On 05/08/2014 09:09 AM, Paolo Bonzini wrote:
> diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
> index a6b7884..e5550e7 100644
> --- a/include/exec/cpu_ldst.h
> +++ b/include/exec/cpu_ldst.h
> @@ -28,8 +28,373 @@
> #ifndef CPU_LDST_H
> #define CPU_LDST_H
>
> -#if !defined(CONFIG_USER_ONLY)
> -#include "exec/softmmu_exec.h"
> +#if defined(CONFIG_USER_ONLY)
> +/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
> +#define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))
As an extremely minor nit, I'd prefer CONFIG_SOFTMMU be the conditional checked
here, so that, as the comment notes, one day we can have CONFIG_SOFTMMU and
CONFIG_USER_ONLY defined at the same time.
r~
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files
2014-05-08 16:09 [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Paolo Bonzini
` (10 preceding siblings ...)
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 11/11] softmmu: move all load/store functions to cpu_ldst.h Paolo Bonzini
@ 2014-05-12 17:37 ` Richard Henderson
11 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2014-05-12 17:37 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel; +Cc: peter.maydell
On 05/08/2014 09:09 AM, Paolo Bonzini wrote:
> This series is a prerequisite for improving the SMAP emulation in
> qemu-system-x86_64. SMAP is a Broadwell feature and testing it in the
> kernel is probably the #1 reason why people are using TCG x86 nowadays.
>
> In order to implement some of the SMAP checks correctly, I need to define
> a new set of ld/st functions, similar to ldl_data but with a different
> definition of cpu_mmu_index. This series lets me do that painlessly,
> by simplifying the set of macros expected by softmmu_header.h. This is
> done by patches 2 to 4.
>
> In addition, implementation of the MMU lookups are spread across all C
> files. There is no reason for this, it can be done in cputlb.c directly.
> This is done by patches 5 to 7.
>
> CPU load/store functions are also split around multiple headers: tcg/tcg.h,
> softmmu_header.h, cpu-all.h, exec-all.h. This series consolidates them
> all in a single header, cpu_ldst.h, in patches 8 to 11.
>
> The only reason why this is RFC is that it depends on TCG backends
> stopping their use of helper_ld*_mmu and using instead the new
> "return-address aware" helpers. With this conversion done, helper_ld*_mmu
> are not anymore TCG-related and it makes sense to move them to cpu_ldst.h.
> The only backends left to convert are S390, with patches on the list,
> and MIPS, which should also get done for 2.1.
Bravo.
Patches 2-11:
Reviewed-by: Richard Henderson <rth@twiddle.net>
I'll make sure I get that mips patch set posted this week; I failed to do that
before going on holiday last week.
r~
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [RFC PATCH 08/11] softmmu: make do_unaligned_access extern
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 08/11] softmmu: make do_unaligned_access extern Paolo Bonzini
@ 2014-05-13 6:53 ` Andreas Färber
2014-05-13 7:08 ` Paolo Bonzini
0 siblings, 1 reply; 22+ messages in thread
From: Andreas Färber @ 2014-05-13 6:53 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel; +Cc: peter.maydell, rth
Am 08.05.2014 18:09, schrieb Paolo Bonzini:
> We will reference it from more files in the next patch.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target-alpha/cpu.h | 3 +++
> target-alpha/mem_helper.c | 4 ++--
> target-mips/cpu.h | 3 +++
> target-mips/op_helper.c | 8 ++------
> target-sparc/cpu.h | 4 ++++
> target-sparc/ldst_helper.c | 9 +++------
> target-xtensa/cpu.h | 3 +++
> target-xtensa/op_helper.c | 5 +----
> 8 files changed, 21 insertions(+), 18 deletions(-)
>
> diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
> index d9b861f..242068f 100644
> --- a/target-alpha/cpu.h
> +++ b/target-alpha/cpu.h
> @@ -498,6 +498,9 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
> *pflags = flags;
> }
>
> +void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
> + int is_write, int is_user, uintptr_t retaddr);
> +
> #include "exec/exec-all.h"
>
> #endif /* !defined (__CPU_ALPHA_H__) */
[snip]
Have you considered turning this into CPUClass hooks instead, as done
with do_unassigned_access?
Before your patch, this was a static function used only by
softmmu_template.h - making it global is not exactly helping with
multi-target support. Any solution to remedy regressions appreciated.
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [RFC PATCH 09/11] target-arm: move arm_*_code to a separate file
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 09/11] target-arm: move arm_*_code to a separate file Paolo Bonzini
@ 2014-05-13 7:03 ` Andreas Färber
2014-05-13 9:05 ` Peter Maydell
0 siblings, 1 reply; 22+ messages in thread
From: Andreas Färber @ 2014-05-13 7:03 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel; +Cc: peter.maydell, Edgar E. Iglesias, rth
Am 08.05.2014 18:09, schrieb Paolo Bonzini:
> These will soon require cpu_ldst.h, so move them out of cpu.h.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target-arm/arm_ldst.h | 47 ++++++++++++++++++++++++++++++++++++++++++++++
> target-arm/cpu.h | 22 ----------------------
> target-arm/helper.c | 1 +
> target-arm/translate-a64.c | 1 +
> target-arm/translate.c | 1 +
> 5 files changed, 50 insertions(+), 22 deletions(-)
> create mode 100644 target-arm/arm_ldst.h
>
> diff --git a/target-arm/arm_ldst.h b/target-arm/arm_ldst.h
> new file mode 100644
> index 0000000..42260ac
> --- /dev/null
> +++ b/target-arm/arm_ldst.h
> @@ -0,0 +1,47 @@
> +/*
> + * ARM load/store instructions for code (armeb-user support)
> + *
> + * Copyright (c) 2012 CodeSourcery, LLC
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef ARM_LDST_H
> +#define ARM_LDST_H
> +
> +#include "qemu/bswap.h"
> +
> +/* Load an instruction and return it in the standard little-endian order */
> +static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
> + bool do_swap)
> +{
> + uint32_t insn = cpu_ldl_code(env, addr);
> + if (do_swap) {
> + return bswap32(insn);
> + }
> + return insn;
> +}
> +
> +/* Ditto, for a halfword (Thumb) instruction */
> +static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
> + bool do_swap)
> +{
> + uint16_t insn = cpu_lduw_code(env, addr);
> + if (do_swap) {
> + return bswap16(insn);
> + }
> + return insn;
> +}
> +
> +#endif
[snip]
Reviewed-by: Andreas Färber <afaerber@suse.de>
I notice that these user-only functions/macros are taking CPUARMState
but never use it today. Should I convert them to CPUState once I tackle
linux-user, or can we just drop that unused argument?
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [RFC PATCH 08/11] softmmu: make do_unaligned_access extern
2014-05-13 6:53 ` Andreas Färber
@ 2014-05-13 7:08 ` Paolo Bonzini
0 siblings, 0 replies; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-13 7:08 UTC (permalink / raw)
To: Andreas Färber, qemu-devel; +Cc: peter.maydell, rth
Il 13/05/2014 08:53, Andreas Färber ha scritto:
>> > +void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
>> > + int is_write, int is_user, uintptr_t retaddr);
>> > +
>> > #include "exec/exec-all.h"
>> >
>> > #endif /* !defined (__CPU_ALPHA_H__) */
> [snip]
>
> Have you considered turning this into CPUClass hooks instead, as done
> with do_unassigned_access?
>
> Before your patch, this was a static function used only by
> softmmu_template.h - making it global is not exactly helping with
> multi-target support. Any solution to remedy regressions appreciated.
Good idea!
Paolo
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [RFC PATCH 11/11] softmmu: move all load/store functions to cpu_ldst.h
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 11/11] softmmu: move all load/store functions to cpu_ldst.h Paolo Bonzini
2014-05-12 17:36 ` Richard Henderson
@ 2014-05-13 7:13 ` Andreas Färber
2014-05-13 7:32 ` Paolo Bonzini
1 sibling, 1 reply; 22+ messages in thread
From: Andreas Färber @ 2014-05-13 7:13 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel; +Cc: peter.maydell, rth
Am 08.05.2014 18:09, schrieb Paolo Bonzini:
> Unify pieces of cpu-all.h, exec-all.h, softmmu_exec.h and tcg/tcg.h
> into a single new header file with all helpers.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> include/exec/cpu-all.h | 119 -------
> include/exec/cpu_ldst.h | 369 ++++++++++++++++++++-
> .../exec/{softmmu_header.h => cpu_ldst_template.h} | 2 +-
> include/exec/exec-all.h | 25 --
> include/exec/softmmu_exec.h | 216 ------------
> tcg/tcg.h | 13 -
> 6 files changed, 368 insertions(+), 376 deletions(-)
> rename include/exec/{softmmu_header.h => cpu_ldst_template.h} (98%)
> delete mode 100644 include/exec/softmmu_exec.h
Seems like a nice cleanup,
Acked-by: Andreas Färber <afaerber@suse.de>
Will rth be handling this along with the backend conversions mentioned
in the cover letter?
Cheers,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [RFC PATCH 11/11] softmmu: move all load/store functions to cpu_ldst.h
2014-05-13 7:13 ` Andreas Färber
@ 2014-05-13 7:32 ` Paolo Bonzini
0 siblings, 0 replies; 22+ messages in thread
From: Paolo Bonzini @ 2014-05-13 7:32 UTC (permalink / raw)
To: Andreas Färber, qemu-devel; +Cc: peter.maydell, rth
Il 13/05/2014 09:13, Andreas Färber ha scritto:
> Am 08.05.2014 18:09, schrieb Paolo Bonzini:
>> Unify pieces of cpu-all.h, exec-all.h, softmmu_exec.h and tcg/tcg.h
>> into a single new header file with all helpers.
>>
>> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>> ---
>> include/exec/cpu-all.h | 119 -------
>> include/exec/cpu_ldst.h | 369 ++++++++++++++++++++-
>> .../exec/{softmmu_header.h => cpu_ldst_template.h} | 2 +-
>> include/exec/exec-all.h | 25 --
>> include/exec/softmmu_exec.h | 216 ------------
>> tcg/tcg.h | 13 -
>> 6 files changed, 368 insertions(+), 376 deletions(-)
>> rename include/exec/{softmmu_header.h => cpu_ldst_template.h} (98%)
>> delete mode 100644 include/exec/softmmu_exec.h
>
> Seems like a nice cleanup,
>
> Acked-by: Andreas Färber <afaerber@suse.de>
>
> Will rth be handling this along with the backend conversions mentioned
> in the cover letter?
I guess so, in the meanwhile I'll send out the ld_raw->ld_p conversion
separately, and the v2 of do_unaligned_access conversion for you to review.
Paolo
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Qemu-devel] [RFC PATCH 09/11] target-arm: move arm_*_code to a separate file
2014-05-13 7:03 ` Andreas Färber
@ 2014-05-13 9:05 ` Peter Maydell
0 siblings, 0 replies; 22+ messages in thread
From: Peter Maydell @ 2014-05-13 9:05 UTC (permalink / raw)
To: Andreas Färber
Cc: Paolo Bonzini, Edgar E. Iglesias, QEMU Developers,
Richard Henderson
On 13 May 2014 08:03, Andreas Färber <afaerber@suse.de> wrote:
> I notice that these user-only functions/macros are taking CPUARMState
> but never use it today. Should I convert them to CPUState once I tackle
> linux-user, or can we just drop that unused argument?
I think they mostly take that argument for consistency with
cpu_ldl_code; we can drop it, I guess.
thanks
-- PMM
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2014-05-13 9:05 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-05-08 16:09 [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 01/11] hw: use ld_p/st_p instead of ld_raw/st_raw Paolo Bonzini
2014-05-09 18:18 ` Peter Maydell
2014-05-09 19:03 ` Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 02/11] softmmu: start introducing SOFTMMU_CODE_ACCESS in softmmu_header.h Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 03/11] softmmu: move MMUSUFFIX under SOFTMMU_CODE_ACCESS Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 04/11] softmmu: move definition of CPU_MMU_INDEX to inclusion site, drop ACCESS_TYPE Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 05/11] softmmu: move ALIGNED_ONLY to cpu.h Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 06/11] softmmu: commonize helper definitions Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 07/11] softmmu: move softmmu_template.h out of include/ Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 08/11] softmmu: make do_unaligned_access extern Paolo Bonzini
2014-05-13 6:53 ` Andreas Färber
2014-05-13 7:08 ` Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 09/11] target-arm: move arm_*_code to a separate file Paolo Bonzini
2014-05-13 7:03 ` Andreas Färber
2014-05-13 9:05 ` Peter Maydell
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 10/11] softmmu: introduce cpu_ldst.h Paolo Bonzini
2014-05-08 16:09 ` [Qemu-devel] [RFC PATCH 11/11] softmmu: move all load/store functions to cpu_ldst.h Paolo Bonzini
2014-05-12 17:36 ` Richard Henderson
2014-05-13 7:13 ` Andreas Färber
2014-05-13 7:32 ` Paolo Bonzini
2014-05-12 17:37 ` [Qemu-devel] [RFC PATCH 00/11] Cleanup load/store functions in headers and C files Richard Henderson
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