From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wk7Cj-0007iV-In for qemu-devel@nongnu.org; Tue, 13 May 2014 03:32:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wk7Cc-0001Yu-Sg for qemu-devel@nongnu.org; Tue, 13 May 2014 03:32:49 -0400 Message-ID: <5371CA98.3030403@suse.de> Date: Tue, 13 May 2014 09:32:40 +0200 From: Alexander Graf MIME-Version: 1.0 References: <1399713400-8619-1-git-send-email-dougkwan@google.com> <1399713400-8619-3-git-send-email-dougkwan@google.com> <5371C44E.8010901@suse.de> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 2/3] PPC: Allow little-endian user mode. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?B?IkRvdWcgS3dhbiAo6Zec5oyv5b63KSI=?= Cc: Riku Voipio , "qemu-ppc@nongnu.org" , QEMU Developers On 13.05.14 09:30, Doug Kwan (=E9=97=9C=E6=8C=AF=E5=BE=B7) wrote: > > > > On Tue, May 13, 2014 at 12:05 AM, Alexander Graf > wrote: > > > On 10.05.14 11:16, Doug Kwan wrote: > > This allow running PPC64 little-endian in user mode if target > is configured > that way. In PPC64 LE user mode we set MSR.LE during > initialization. > Overhaul handling of byteswapping in code generation and mem > helpers. > > Signed-off-by: Doug Kwan > > --- > target-ppc/mem_helper.c | 25 ++++++-- > target-ppc/translate.c | 150 > +++++++++++++++++--------------------------- > target-ppc/translate_init.c | 9 +++ > 3 files changed, 89 insertions(+), 95 deletions(-) > > > [...] > > > diff --git a/target-ppc/translate_init.c > b/target-ppc/translate_init.c > index 4d94015..84381ae 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -8418,6 +8418,9 @@ static void ppc_cpu_reset(CPUState *s) > msr |=3D (target_ulong)1 << MSR_VR; /* Allow altivec usag= e */ > msr |=3D (target_ulong)1 << MSR_SPE; /* Allow SPE usage *= / > msr |=3D (target_ulong)1 << MSR_PR; > +#if !defined(TARGET_WORDS_BIGENDIAN) > + msr |=3D (target_ulong)1 << MSR_LE; /* Little-endian user > mode */ > +#endif > #endif > #if defined(TARGET_PPC64) > @@ -8461,6 +8464,12 @@ static void ppc_cpu_reset(CPUState *s) > /* Flush all TLBs */ > tlb_flush(s, 1); > + > +#if defined(CONFIG_USER_ONLY) && !defined(TARGET_WORDS_BIGENDI= AN) > + if (!msr_le) { > + cpu_abort(CPU(cpu), "Cannot set QEMU to little-endian > user mode\n"); > > > We don't have this check the other way around, so why do we need > it here? How do you ever get to this? > > > Alex > > I am just being paranoid as I am new to this code base. The reason=20 > why this is asymmetric because the PPC targets are big-endian by=20 > default and I don't know if all CPUs support setting msr.le. If=20 > someone specifies a CPU that does not support little-endian mode, I=20 > want to stop qemu early with an error. The check can be removed if it=20 > is redundant. Well, all CPUs that Linux supports with LE today also support the MSR_LE=20 bit. If anyone would ever want to do an e500 LE port things would become=20 messy, as LE is a TLB property there, so we don't have a generic bit to=20 look at. I think we just drop this check. If the user passes in an incompatible=20 CPU it's his own fault :). Alex