Re: [Qemu-devel] [PATCH] SMI handler should set the CPL to zero and save and restore it on rsm.

[Paolo Bonzini <pbonzini@redhat.com>]

Il 13/05/2014 20:39, Kevin O'Connor ha scritto:
> On Tue, May 13, 2014 at 08:24:47PM +0200, Paolo Bonzini wrote:
>> Il 27/04/2014 19:25, Kevin O'Connor ha scritto:
>>> I was wondering about that as well.  The Intel docs state that the CPL
>>> is bits 0-1 of the CS.selector register, and that protected mode
>>> starts immediately after setting the PE bit.  The CS.selector field
>>> should be the value of %cs in real mode, which is the value added to
>>> eip (after shifting right by 4).
>>>
>>> I guess that means that the real mode code that enables the PE bit
>>> must run with a code segment aligned to a value of 4.  (Which
>>> effectively means code alignment of 64 bytes because of the segment
>>> shift.)
>>
>> It turns out that this is not a requirement; which means that the
>> protected mode transition is exactly the only place where CPL is not
>> redundant.  The CPL remains zero until you reload CS with a long jump.
>
> That doesn't sound right.  What happens if the processor takes an NMI,
> SMI, or VMEXIT between the point it enables protected mode but before
> it long jumps?  The processor would have to save and restore the CPL
> somewhere for all of these situations.

For VMEXITs it's up to the hypervisor to make it work properly.  I just 
posted today fixes for KVM.

I guess the answer for NMIs is "good luck".  But in the case of NMIs, 
wouldn't it be broken anyway, because the IDT format is different 
between real mode and protected mode?

For SMIs, http://www.sandpile.org/x86/smm.htm says that the CPL is 
stored somewhere in SMRAM.  I think your patches are an improvement 
anyway, we can build a more complete fix on top of them.

Paolo

> If you are right, I think the whole series needs to be reworked.