qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Sergey Fedorov <serge.fdrv@gmail.com>
To: Fabian Aggeler <aggelerf@ethz.ch>, qemu-devel@nongnu.org
Cc: edgar.iglesias@gmail.com, Sergey Fedorov <s.fedorov@samsung.com>,
	peter.maydell@linaro.org
Subject: Re: [Qemu-devel] [PATCH v2 06/23] target-arm: add arm_is_secure() function
Date: Wed, 14 May 2014 09:53:12 +0400	[thread overview]
Message-ID: <537304C8.1030407@gmail.com> (raw)
In-Reply-To: <1399997768-32014-7-git-send-email-aggelerf@ethz.ch>

On 13.05.2014 20:15, Fabian Aggeler wrote:
> arm_is_secure() function allows to determine CPU security state
> if the CPU implements Security Extensions.
>
> Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
> ---
>  target-arm/cpu.h | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index a56d3d6..6ea0432 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -640,6 +640,21 @@ static inline int arm_feature(CPUARMState *env, int feature)
>      return (env->features & (1ULL << feature)) != 0;
>  }
>  
> +/* Return true if the processor is in secure state */
> +static inline bool arm_is_secure(CPUARMState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> +    if (arm_feature(env, ARM_FEATURE_SECURITY_EXTENSIONS)) {

I think feature test can be safely avoided here. Without this feature
that should be no way to switch to monitor mode and to access SCR register.

> +        return ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) ||
> +                !(env->cp15.c1_scr & 1);
> +    } else {
> +        return false;
> +    }
> +#else
> +    return false;

That is a good question how to treat user emulation: secure or
non-secure. Perhaps assuming user emulation in secure state may simplify
code in the following patches.

> +#endif
> +}
> +
>  /* Return true if the specified exception level is running in AArch64 state. */
>  static inline bool arm_el_is_aa64(CPUARMState *env, int el)
>  {

Thanks,
Sergey.

  reply	other threads:[~2014-05-14  5:53 UTC|newest]

Thread overview: 75+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-13 16:15 [Qemu-devel] [PATCH v2 00/23] target-arm: add Security Extensions for CPUs Fabian Aggeler
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 01/23] target-arm: add new CPU feature for Security Extensions Fabian Aggeler
2014-05-21 14:46   ` Peter Maydell
2014-05-21 16:14     ` Christopher Covington
2014-05-21 16:33       ` Sergey Fedorov
2014-05-21 16:41         ` Peter Maydell
2014-05-21 16:47           ` Sergey Fedorov
2014-05-21 14:51   ` Peter Maydell
2014-05-22  9:09     ` Aggeler  Fabian
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 02/23] target-arm: move SCR into Security Extensions register list Fabian Aggeler
2014-05-14 14:19   ` Greg Bellows
2014-05-15  9:28     ` Aggeler  Fabian
2014-05-21 14:57   ` Peter Maydell
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 03/23] target-arm: adjust TTBCR for Security Extension feature Fabian Aggeler
2014-05-21 16:06   ` Peter Maydell
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 04/23] target-arm: preserve RAO/WI bits of ARMv7 SCTLR Fabian Aggeler
2014-05-14  5:43   ` Sergey Fedorov
2014-05-21 16:12     ` Peter Maydell
2014-05-22  8:58       ` Aggeler  Fabian
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 05/23] target-arm: add CPU Monitor mode Fabian Aggeler
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 06/23] target-arm: add arm_is_secure() function Fabian Aggeler
2014-05-14  5:53   ` Sergey Fedorov [this message]
2014-05-14 14:42     ` Greg Bellows
2014-05-14 18:35       ` Fedorov Sergey
2014-05-14 20:22         ` Greg Bellows
2014-05-14 21:29           ` Peter Maydell
2014-05-14 22:22             ` Greg Bellows
2014-05-15 13:00               ` Aggeler  Fabian
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 07/23] target-arm: reject switching to monitor mode from non-secure state Fabian Aggeler
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 08/23] target-arm: adjust arm_current_pl() for Security Extensions Fabian Aggeler
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 09/23] target-arm: add non-secure Translation Block flag Fabian Aggeler
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 10/23] target-arm: implement CPACR register logic Fabian Aggeler
2014-05-14  6:06   ` Sergey Fedorov
2014-05-14 18:39     ` Fedorov Sergey
2014-05-15 14:44       ` Fabian Aggeler
2014-05-15 15:06         ` Sergey Fedorov
2014-05-14 13:09   ` Peter Crosthwaite
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 11/23] target-arm: add NSACR support Fabian Aggeler
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 12/23] target-arm: add SDER definition Fabian Aggeler
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 13/23] target-arm: Split TLB for secure state and EL3 in Aarch64 Fabian Aggeler
2014-05-14  6:15   ` Sergey Fedorov
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 14/23] target-arm: add banked coprocessor register type and macros Fabian Aggeler
2014-05-14 16:42   ` Greg Bellows
2014-05-15  9:02     ` Aggeler  Fabian
2014-05-15 18:42   ` Sergey Fedorov
2014-05-15 19:10     ` Aggeler  Fabian
2014-05-16  7:06       ` Sergey Fedorov
2014-05-22  7:41   ` Edgar E. Iglesias
2014-05-22 11:49     ` Aggeler  Fabian
2014-05-22 12:18       ` Sergey Fedorov
2014-05-22 12:50         ` Aggeler  Fabian
2014-05-22 22:21           ` Greg Bellows
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 15/23] target-arm: Restrict EL3 to Aarch32 state Fabian Aggeler
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 16/23] target-arm: Use arm_current_sctlr to access SCTLR Fabian Aggeler
2014-05-22  7:33   ` Edgar E. Iglesias
2014-05-22 14:56     ` Aggeler  Fabian
2014-05-22 21:24       ` Edgar E. Iglesias
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 17/23] target-arm: Use raw_write/raw_read whenever possible Fabian Aggeler
2014-05-14 17:32   ` Greg Bellows
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 18/23] target-arm: Convert banked coprocessor registers Fabian Aggeler
2014-05-14 19:47   ` Greg Bellows
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 19/23] target-arm: maintain common bits of banked CP registers Fabian Aggeler
2014-05-14 21:20   ` Greg Bellows
2014-05-15 13:10     ` Aggeler  Fabian
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 20/23] target-arm: add MVBAR support Fabian Aggeler
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 21/23] target-arm: implement SMC instruction Fabian Aggeler
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 22/23] target-arm: implement IRQ/FIQ routing to Monitor mode Fabian Aggeler
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 23/23] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI Fabian Aggeler
2014-05-15 18:57 ` [Qemu-devel] [PATCH v2 00/23] target-arm: add Security Extensions for CPUs Sergey Fedorov
2014-05-16  6:00   ` Aggeler  Fabian
2014-05-16 20:56     ` Greg Bellows
2014-05-20 10:00       ` Aggeler  Fabian
2014-05-20 15:43         ` Greg Bellows
2014-05-21 14:04           ` Peter Maydell
2014-05-21 13:55       ` Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=537304C8.1030407@gmail.com \
    --to=serge.fdrv@gmail.com \
    --cc=aggelerf@ethz.ch \
    --cc=edgar.iglesias@gmail.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=s.fedorov@samsung.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).