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Date: Thu, 15 May 2014 19:06:50 +0400
From: Sergey Fedorov <serge.fdrv@gmail.com>
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Subject: Re: [Qemu-devel] [PATCH v2 10/23] target-arm: implement CPACR
 register logic
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To: Fabian Aggeler <aggelerf@ethz.ch>, qemu-devel@nongnu.org
Cc: edgar.iglesias@gmail.com, Sergey Fedorov <s.fedorov@samsung.com>, peter.maydell@linaro.org


On 15.05.2014 18:44, Fabian Aggeler wrote:
>>> Please, look at disas_vfp_insn() and disas_neon_*_insn() functions.
>>> Looks like them should be updated. In that case do not forget to adjust
>>> arm_cpu_reset() so user emulation would be able to execute VFP/NEON
>>> instructions.
>>
>> See ARM ARM v7-AR B1.11.1
>>
>
> I don't quite get what you mean. Bits 20-24 of c1_coproc already get
> set to 1 for user emulation in arm_cpu_reset(). And disas_cfp_insn and
> disas_neon_*_insn() all check s->cpacr_fpen in the beginning (which
> gets set in cpu_get_tb_cpu_state() if bits 20-22 of c1_coproc are set
> to 3 or (1 && cpu is in user mode)).
>
> So I guess we should add some checks for NSACR, to only set that flag
> if the corresponding NSACR bit is set.

Sorry, you are right.

Regards,
Sergey.