From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60376) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wlj4r-0003Kz-70 for qemu-devel@nongnu.org; Sat, 17 May 2014 14:11:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wlj4i-0000gG-61 for qemu-devel@nongnu.org; Sat, 17 May 2014 14:11:21 -0400 Received: from mail-ie0-x233.google.com ([2607:f8b0:4001:c03::233]:61083) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wlj4i-0000gC-0p for qemu-devel@nongnu.org; Sat, 17 May 2014 14:11:12 -0400 Received: by mail-ie0-f179.google.com with SMTP id rd18so570250iec.38 for ; Sat, 17 May 2014 11:11:11 -0700 (PDT) Sender: Richard Henderson Message-ID: <5377A63B.7050308@twiddle.net> Date: Sat, 17 May 2014 11:11:07 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1400264014-78911-1-git-send-email-petar.jovanovic@rt-rk.com> <1400264014-78911-3-git-send-email-petar.jovanovic@rt-rk.com> In-Reply-To: <1400264014-78911-3-git-send-email-petar.jovanovic@rt-rk.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 2/2] target-mips: implement UserLocal Register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Petar Jovanovic , qemu-devel@nongnu.org Cc: petar.jovanovic@imgtec.com, aurelien@aurel32.net On 05/16/2014 11:13 AM, Petar Jovanovic wrote: > +target_ulong helper_rdhwr_ul(CPUMIPSState *env) > +{ > + if ((env->hflags & MIPS_HFLAG_CP0) || > + (env->CP0_HWREna & (1 << 29))) { > + return env->CP0_UserLocal; > + } else { > + helper_raise_exception(env, EXCP_RI); > + } > + > + return 0; > +} > + You shouldn't need a helper at all. We're supposed to check all of these sorts of permissions at translation time, so you should be able to issue a load or an exception directly from the translator. > + if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { What is this check, and why isn't it present in ctx->hflags? > + tcg_gen_ld_tl(arg, cpu_env, > + offsetof(CPUMIPSState, CP0_UserLocal)); > + tcg_gen_ext32s_tl(arg, arg); One operation: tcg_gen_ld32s_tl. > #else > - /* XXX: Some CPUs implement this in hardware. > - Not supported yet. */ > + save_cpu_state(ctx, 1); > + gen_helper_rdhwr_ul(t0, cpu_env); > + gen_store_gpr(t0, rt); > + break; > #endif > This should be at least partially merged with the user-only tls_value code. r~