From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57695) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WmkSQ-0002VL-8A for qemu-devel@nongnu.org; Tue, 20 May 2014 09:52:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WmkSI-0003qT-AL for qemu-devel@nongnu.org; Tue, 20 May 2014 09:51:54 -0400 Received: from cantor2.suse.de ([195.135.220.15]:37993 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WmkSI-0003qF-4g for qemu-devel@nongnu.org; Tue, 20 May 2014 09:51:46 -0400 Message-ID: <537B5DEE.2090205@suse.de> Date: Tue, 20 May 2014 15:51:42 +0200 From: Alexander Graf MIME-Version: 1.0 References: <1400491383-6725-1-git-send-email-edgar.iglesias@gmail.com> <1400491383-6725-23-git-send-email-edgar.iglesias@gmail.com> <20140520132846.GJ18802@zapo.iiNet> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v3 22/22] RFC: target-arm: Use a 1:1 mapping between EL and MMU index List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , "Edgar E. Iglesias" Cc: "rob.herring@linaro.org" , "peter.crosthwaite@xilinx.com" , Aggeler Fabian , "qemu-devel@nongnu.org" , "john.williams@xilinx.com" , "alex.bennee@linaro.org" , "christoffer.dall@linaro.org" , "rth@twiddle.net" On 20.05.14 15:47, Peter Maydell wrote: > On 20 May 2014 14:28, Edgar E. Iglesias wrot= e: >> On Tue, May 20, 2014 at 09:47:47AM +0000, Aggeler Fabian wrote: >>> I guess this makes sense. Shouldn=E2=80=99t we implement two more MMU= s to separate S-EL0/EL0 and S-EL1/EL1 >>> at least for ARMv8 with EL3 running in Aarch64 state? >> Maybe with future patches. My understanding is that on aarch64 the wor= ld >> switch between S/NS requires EL3 firmware to reprogram the TTBR regs. >> Currently in QEMU, the re-programming of TTBR will flush the TLBs. We = would >> need to do something about that before adding MMU tables for aarch64 S= ecure >> EL0/1 does any good. I think it's better to keep it simple for now and= leave >> this as a possible future optimization. >> >> Another possible future optimization is to add some kind of dynamic al= location >> of a limited set of MMU tables for different ASIDs and VMIDs. For emul= ated >> virtualization, it might help quite a bit. > I think the right way to do that is to have QEMU's TLB > structure include some sort of general equivalent to the > ASID/VMID mechanism (presumably other target CPUs have some > equivalent). Then we can honour 'flush by ASID' as well. > (We make a forlorn gesture in this direction with the > completely ignored 'flush_global' parameter to tlb_flush().) I tried to implement this a few years ago, but utterly failed. If=20 anyone's interested I can probably dig out the patches I had :). Alex