From: Alexey Kardashevskiy <aik@ozlabs.ru>
To: Alexander Graf <agraf@suse.de>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v2 8/8] spapr_pci: Use XICS interrupt allocator and do not cache interrupts in PHB
Date: Wed, 21 May 2014 18:52:52 +1000 [thread overview]
Message-ID: <537C6964.2050708@ozlabs.ru> (raw)
In-Reply-To: <537C6680.20601@suse.de>
On 05/21/2014 06:40 PM, Alexander Graf wrote:
>
> On 15.05.14 11:59, Alexey Kardashevskiy wrote:
>> Currently SPAPR PHB keeps track of all allocated MSI/MISX interrupt as
>> XICS used to be unable to reuse interrupts which becomes a problem for
>> dynamic MSI reconfiguration which is happening on guest driver reload or
>> PCI hot (un)plug. Another problem is that PHB has a limit of devices
>> supporting MSI/MSIX (SPAPR_MSIX_MAX_DEVS=32) and there is no good reason
>> for that.
>>
>> This makes use of new XICS ability to reuse interrupts.
>>
>> This removes cached MSI configuration from SPAPR PHB so the first IRQ number
>> of a device is stored in MSI/MSIX config space so there is no need to store
>> this anywhere else. From now on, SPAPR PHB only keeps flags telling what
>> type
>> of interrupt for which device it has configured in order to return error if
>> (for example) MSIX was enabled and the guest is trying to disable MSI which
>> it has not enabled.
>>
>> This removes a limit for the maximum number of MSIX-enabled devices per PHB,
>> now XICS and PCI bus capacity are the only limitation.
>>
>> This changes migration stream as it fixes vmstate_spapr_pci_msi::name
>> which was
>> wrong since the beginning.
>>
>> This fixed traces to be more informative.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>>
>> In reality either MSIX or MSI is enabled, never both. So I could remove
>> msi/msix
>> bitmaps from this patch, would it make sense?
>
> Is this a hard requirement? Does a device have to choose between MSIX and
> MSI or could it theoretically have both enabled? Is this a PCI limitation,
> a PAPR/XICS limitation or just a limitation of your implementation?
My implementation does not have this limitation, I asked if I can simplify
code by introducing one :)
I cannot see any reason why PCI cannot have both MSI and MSIX enabled but
it does not seem to be used by anyone => cannot debug and confirm.
PAPR spec assumes that if the guest tries enabling MSIX when MSI is already
enabled, this is a "change", not enabling both types. But it also says MSI
and MSIX vector numbers are not shared. Hm.
--
Alexey
next prev parent reply other threads:[~2014-05-21 8:53 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-15 9:59 [Qemu-devel] [PATCH v2 0/8] Move interrupts from spapr to xics Alexey Kardashevskiy
2014-05-15 9:59 ` [Qemu-devel] [PATCH v2 1/8] xics: Add flags for interrupts Alexey Kardashevskiy
2014-05-21 6:30 ` Alexey Kardashevskiy
2014-05-21 8:40 ` Alexander Graf
2014-05-15 9:59 ` [Qemu-devel] [PATCH v2 2/8] xics: Add xics_find_source() Alexey Kardashevskiy
2014-05-15 9:59 ` [Qemu-devel] [PATCH v2 3/8] xics: Disable flags reset on xics reset Alexey Kardashevskiy
2014-05-15 9:59 ` [Qemu-devel] [PATCH v2 4/8] spapr: Move interrupt allocator to xics Alexey Kardashevskiy
2014-05-21 8:34 ` Alexander Graf
2014-05-21 8:46 ` Alexey Kardashevskiy
2014-05-21 8:47 ` Alexander Graf
2014-05-15 9:59 ` [Qemu-devel] [PATCH v2 5/8] xics: Remove obsolete xics_set_irq_type() Alexey Kardashevskiy
2014-05-15 9:59 ` [Qemu-devel] [PATCH v2 6/8] spapr: Remove @next_irq Alexey Kardashevskiy
2014-05-15 9:59 ` [Qemu-devel] [PATCH v2 7/8] xics: Implement xics_ics_free() Alexey Kardashevskiy
2014-05-15 9:59 ` [Qemu-devel] [PATCH v2 8/8] spapr_pci: Use XICS interrupt allocator and do not cache interrupts in PHB Alexey Kardashevskiy
2014-05-21 8:40 ` Alexander Graf
2014-05-21 8:52 ` Alexey Kardashevskiy [this message]
2014-05-21 9:06 ` Alexander Graf
2014-05-21 9:11 ` Michael S. Tsirkin
2014-05-21 9:13 ` Alexander Graf
2014-05-21 9:33 ` Alexey Kardashevskiy
2014-05-21 9:38 ` Michael S. Tsirkin
2014-05-21 10:03 ` Alexey Kardashevskiy
2014-05-21 9:50 ` Alexander Graf
2014-05-21 10:13 ` Alexey Kardashevskiy
2014-05-21 10:35 ` Alexander Graf
2014-05-21 12:42 ` Alexey Kardashevskiy
2014-05-22 6:53 ` Alexey Kardashevskiy
2014-05-22 7:16 ` Alexander Graf
2014-05-22 10:53 ` Alexey Kardashevskiy
2014-05-22 10:53 ` [Qemu-devel] [PATCH 1/2] vmstate: Add helper to enable GHashTable migration Alexey Kardashevskiy
2014-05-22 10:57 ` Alexander Graf
2014-05-22 11:04 ` Alexey Kardashevskiy
2014-05-22 10:53 ` [Qemu-devel] [PATCH 2/2] spapr_pci: Use XICS interrupt allocator and do not cache interrupts in PHB Alexey Kardashevskiy
2014-05-22 10:57 ` [Qemu-devel] [PATCH v2 8/8] " Alexander Graf
2014-05-22 14:25 ` Alexey Kardashevskiy
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=537C6964.2050708@ozlabs.ru \
--to=aik@ozlabs.ru \
--cc=agraf@suse.de \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).