From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53285) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wn44N-0008Cc-VY for qemu-devel@nongnu.org; Wed, 21 May 2014 06:48:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wn43j-0003in-3J for qemu-devel@nongnu.org; Wed, 21 May 2014 06:48:23 -0400 Message-ID: <537C844D.4080200@suse.de> Date: Wed, 21 May 2014 12:47:41 +0200 From: Alexander Graf MIME-Version: 1.0 References: <1400653228-31540-1-git-send-email-aik@ozlabs.ru> <1400653228-31540-6-git-send-email-aik@ozlabs.ru> In-Reply-To: <1400653228-31540-6-git-send-email-aik@ozlabs.ru> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 5/9] target-ppc: Add POWER8 SPRs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy , qemu-devel@nongnu.org Cc: Tom Musta , qemu-ppc@nongnu.org On 21.05.14 08:20, Alexey Kardashevskiy wrote: > This adds helper which adds TAR/BESCRS/BESCRSU/BESCRR/BESCRRU/ > EBBHR/EBBRR/BESCR/TFHAR/TFIAR/TEXASR/TEXASRU SPRs. > > This adds MMCR2/FSCR/MMCRS SPRs. > > Signed-off-by: Alexey Kardashevskiy > --- > target-ppc/cpu.h | 15 ++++++ > target-ppc/translate_init.c | 123 ++++++++++++++++++++++++++++++++++---------- > 2 files changed, 112 insertions(+), 26 deletions(-) > > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index 262cf0f..72ed763 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -1258,6 +1258,10 @@ static inline int cpu_mmu_index (CPUPPCState *env) > #define SPR_MPC_EIE (0x050) > #define SPR_MPC_EID (0x051) > #define SPR_MPC_NRI (0x052) > +#define SPR_TFHAR (0x080) > +#define SPR_TFIAR (0x081) > +#define SPR_TEXASR (0x082) > +#define SPR_TEXASRU (0x083) > #define SPR_UCTRL (0x088) > #define SPR_MPC_CMPA (0x090) > #define SPR_MPC_CMPB (0x091) > @@ -1270,6 +1274,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) > #define SPR_CTRL (0x098) > #define SPR_MPC_CMPE (0x098) > #define SPR_MPC_CMPF (0x099) > +#define SPR_FSCR (0x099) > #define SPR_MPC_CMPG (0x09A) > #define SPR_MPC_CMPH (0x09B) > #define SPR_MPC_LCTRL1 (0x09C) > @@ -1461,6 +1466,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) > #define SPR_MPC_MI_CTR (0x300) > #define SPR_PERF1 (0x301) > #define SPR_RCPU_MI_RBA1 (0x301) > +#define SPR_POWER_UMMCR2 (0x301) > #define SPR_PERF2 (0x302) > #define SPR_RCPU_MI_RBA2 (0x302) > #define SPR_MPC_MI_AP (0x302) > @@ -1500,6 +1506,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) > #define SPR_MPC_MD_TW (0x30F) > #define SPR_UPERF0 (0x310) > #define SPR_UPERF1 (0x311) > +#define SPR_POWER_MMCR2 (0x311) > #define SPR_UPERF2 (0x312) > #define SPR_MMCRA (0x312) > #define SPR_UPERF3 (0x313) > @@ -1519,11 +1526,18 @@ static inline int cpu_mmu_index (CPUPPCState *env) > #define SPR_UPERFF (0x31F) > #define SPR_RCPU_MI_RA0 (0x320) > #define SPR_MPC_MI_DBCAM (0x320) > +#define SPR_BESCRS (0x320) > #define SPR_RCPU_MI_RA1 (0x321) > #define SPR_MPC_MI_DBRAM0 (0x321) > +#define SPR_BESCRSU (0x321) > #define SPR_RCPU_MI_RA2 (0x322) > #define SPR_MPC_MI_DBRAM1 (0x322) > +#define SPR_BESCRR (0x322) > #define SPR_RCPU_MI_RA3 (0x323) > +#define SPR_BESCRRU (0x323) > +#define SPR_EBBHR (0x324) > +#define SPR_EBBRR (0x325) > +#define SPR_BESCR (0x326) > #define SPR_RCPU_L2U_RA0 (0x328) > #define SPR_MPC_MD_DBCAM (0x328) > #define SPR_RCPU_L2U_RA1 (0x329) > @@ -1542,6 +1556,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) > #define SPR_440_ITV3 (0x377) > #define SPR_440_CCR1 (0x378) > #define SPR_DCRIPR (0x37B) > +#define SPR_MMCRS (0x37E) > #define SPR_PPR (0x380) > #define SPR_750_GQR0 (0x390) > #define SPR_440_DNV0 (0x390) > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 3c37e93..d23fcc6 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -7951,37 +7951,108 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data) > pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; > } > > -static void init_proc_POWER8(CPUPPCState *env) > +static void get_spr_power8_branch_control(CPUPPCState *env) > { > - gen_spr_ne_601(env); > - gen_spr_7xx(env); > - /* Time base */ > - gen_tbl(env); > - gen_spr_book3s_ids(env); > - gen_spr_book3s_common(env); > - gen_spr_amr(env); > - gen_spr_book3s_vr(env); > - gen_spr_book3s_lpar(env); > - gen_spr_book3s_purr(env); > - gen_spr_book3s_debug(env); > - gen_spr_book3s_pmu(env); > -#if !defined(CONFIG_USER_ONLY) > - env->slb_nr = 32; > -#endif /* !CONFIG_USER_ONLY */ > - init_excp_POWER7(env); > - env->dcache_line_size = 128; > - env->icache_line_size = 128; > - > - /* Allocate hardware IRQ controller */ > - ppcPOWER7_irq_init(env); > - /* Can't find information on what this should be on reset. This > - * value is the one used by 74xx processors. */ > - vscr_init(env, 0x00010000); > - > spr_register(env, SPR_TAR, "TAR", > &spr_read_generic, &spr_write_generic, > &spr_read_generic, &spr_write_generic, > 0x00000000); > + > + spr_register(env, SPR_BESCRS, "BESCRS", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, Please introduce a special helper for these that checks whether FSCR.EBB == 1 and injects a facility interrupt if not. Alex