From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56566) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WnRLC-00014t-3L for qemu-devel@nongnu.org; Thu, 22 May 2014 07:39:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WnRL2-0004Xw-Cv for qemu-devel@nongnu.org; Thu, 22 May 2014 07:39:18 -0400 Message-ID: <537DE1DA.1060005@gmail.com> Date: Thu, 22 May 2014 06:39:06 -0500 From: Tom Musta MIME-Version: 1.0 References: <1400653228-31540-1-git-send-email-aik@ozlabs.ru> <1400653228-31540-8-git-send-email-aik@ozlabs.ru> <537CEC67.3000305@gmail.com> <537D65FB.7040007@ozlabs.ru> In-Reply-To: <537D65FB.7040007@ozlabs.ru> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 7/9] KVM: target-ppc: Enable transactional state migration List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Alexander Graf On 5/21/2014 9:50 PM, Alexey Kardashevskiy wrote: > On 05/22/2014 04:11 AM, Tom Musta wrote: >> On 5/21/2014 1:20 AM, Alexey Kardashevskiy wrote: >>> This adds migration support for registers saved before transaction started. >>> [ ... ] >> >> > >> TM is not limited in the ISA to 64-bit implementations. Why restrict >> this to TARGET_PPC64? > > TS/TM bits in MSR are in top 32bits which are unavailable for 32bit > machine, and we are emulating a machine here, this is pretty much why. > > OK. This makes more sense to me now. Thanks.