From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42441) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wntw1-0005iO-UL for qemu-devel@nongnu.org; Fri, 23 May 2014 14:11:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wntvs-0000mR-T3 for qemu-devel@nongnu.org; Fri, 23 May 2014 14:11:13 -0400 Received: from mail-ee0-x231.google.com ([2a00:1450:4013:c00::231]:37690) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wntvs-0000mJ-MR for qemu-devel@nongnu.org; Fri, 23 May 2014 14:11:04 -0400 Received: by mail-ee0-f49.google.com with SMTP id e53so3810507eek.8 for ; Fri, 23 May 2014 11:11:03 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <537F8F32.40305@redhat.com> Date: Fri, 23 May 2014 20:10:58 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1399041202-26184-1-git-send-email-pbonzini@redhat.com> <1399041202-26184-7-git-send-email-pbonzini@redhat.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 6/8] cpu: make CPU_INTERRUPT_RESET available on all targets List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers Il 23/05/2014 19:59, Peter Maydell ha scritto: > On 2 May 2014 15:33, Paolo Bonzini wrote: >> On the x86, some devices need access to the CPU reset pin (INIT#). >> Provide a generic service to do this, using one of the internal >> cpu_interrupt targets. Generalize the PPC-specific code for >> CPU_INTERRUPT_RESET to other targets. >> >> Since PPC does not support migration across QEMU versions (its >> machine types are not versioned yet), I picked the value that >> is used on x86, CPU_INTERRUPT_TGT_INT_1. Consequently, TGT_INT_2 >> and TGT_INT_3 are shifted down by one while keeping their value. >> >> Reviewed-by: Anthony Liguori >> Signed-off-by: Paolo Bonzini >> --- >> cpu-exec.c | 23 +++++++++++++---------- >> cpus.c | 9 +++++++++ >> include/exec/cpu-all.h | 8 +++++--- >> include/sysemu/cpus.h | 1 + >> target-i386/cpu.h | 7 ++++--- >> target-ppc/cpu.h | 3 --- >> 6 files changed, 32 insertions(+), 19 deletions(-) >> >> diff --git a/cpu-exec.c b/cpu-exec.c >> index 2f54054..38e5f02 100644 >> --- a/cpu-exec.c >> +++ b/cpu-exec.c >> @@ -336,19 +336,25 @@ int cpu_exec(CPUArchState *env) >> } >> #endif >> #if defined(TARGET_I386) >> + if (interrupt_request & CPU_INTERRUPT_INIT) { >> + cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0); >> + do_cpu_init(x86_cpu); >> + cpu->exception_index = EXCP_HALTED; >> + cpu_loop_exit(cpu); >> + } >> +#else >> + if (interrupt_request & CPU_INTERRUPT_RESET) { >> + cpu_reset(cpu); >> + } >> +#endif > > I was looking at cleaning up the horrible ifdef ladder a little > lower in this function, and I noticed this code had been > added recently. Why is TARGET_I386 a special case here? Because a hypervisor (cpu_svm_check_intercept_param) can block the interrupt. Note that CPU_INTERRUPT_INIT is actually the same bit as CPU_INTERRUPT_RESET. The whole #ifdef mess should probably be changed to a function in cpu.c, now that we don't have AREG0 constraints anymore. Paolo