From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WnvQS-0005s9-Bi for qemu-devel@nongnu.org; Fri, 23 May 2014 15:46:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WnvQM-00006e-Aw for qemu-devel@nongnu.org; Fri, 23 May 2014 15:46:44 -0400 Received: from mail-ee0-x22c.google.com ([2a00:1450:4013:c00::22c]:60409) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WnvQL-00006Z-Vr for qemu-devel@nongnu.org; Fri, 23 May 2014 15:46:38 -0400 Received: by mail-ee0-f44.google.com with SMTP id c41so4073333eek.3 for ; Fri, 23 May 2014 12:46:36 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <537FA597.3050703@redhat.com> Date: Fri, 23 May 2014 21:46:31 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1400871431-12655-1-git-send-email-rth@twiddle.net> <1400871431-12655-3-git-send-email-rth@twiddle.net> In-Reply-To: <1400871431-12655-3-git-send-email-rth@twiddle.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 2/2] tcg/optimize: Remember garbage high bits for 32-bit ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , qemu-devel@nongnu.org Cc: aurelien@aurel32.net, HPENNER@de.ibm.com Il 23/05/2014 20:57, Richard Henderson ha scritto: > For a 64-bit host, the high bits of a register after a 32-bit operation > are undefined. Adjust the temps mask for all 32-bit ops to reflect that. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 33 ++++++++++++++++++++++++++------- > 1 file changed, 26 insertions(+), 7 deletions(-) > > diff --git a/tcg/optimize.c b/tcg/optimize.c > index 83e1387..19e4831 100644 > --- a/tcg/optimize.c > +++ b/tcg/optimize.c > @@ -166,11 +166,18 @@ static void tcg_opt_gen_mov(TCGContext *s, int op_index, TCGArg *gen_args, > TCGOpcode old_op, TCGArg dst, TCGArg src) > { > TCGOpcode new_op = op_to_mov(old_op); > + tcg_target_ulong mask; > > s->gen_opc_buf[op_index] = new_op; > > reset_temp(dst); > - temps[dst].mask = temps[src].mask; > + mask = temps[src].mask; > + if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) { > + /* High bits of the destination are now garbage. */ Or they are zero on x86_64... perhaps this could be some kind of TCG target hook. > + mask |= ~0xffffffffull; > + } > + temps[dst].mask = mask; > + > assert(temps[src].state != TCG_TEMP_CONST); > > if (s->temps[src].type == s->temps[dst].type) { > @@ -194,13 +201,20 @@ static void tcg_opt_gen_movi(TCGContext *s, int op_index, TCGArg *gen_args, > TCGOpcode old_op, TCGArg dst, TCGArg val) > { > TCGOpcode new_op = op_to_movi(old_op); > + tcg_target_ulong mask; > > s->gen_opc_buf[op_index] = new_op; > > reset_temp(dst); > temps[dst].state = TCG_TEMP_CONST; > temps[dst].val = val; > - temps[dst].mask = val; > + mask = val; > + if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) { > + /* High bits of the destination are now garbage. */ > + mask |= ~0xffffffffull; > + } > + temps[dst].mask = mask; > + > gen_args[0] = dst; > gen_args[1] = val; > } > @@ -539,7 +553,7 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, > for (op_index = 0; op_index < nb_ops; op_index++) { > TCGOpcode op = s->gen_opc_buf[op_index]; > const TCGOpDef *def = &tcg_op_defs[op]; > - tcg_target_ulong mask, affected; > + tcg_target_ulong mask, partmask, affected; > int nb_oargs, nb_iargs, nb_args, i; > TCGArg tmp; > > @@ -901,13 +915,18 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, > break; > } > > - /* 32-bit ops (non 64-bit ops and non load/store ops) generate 32-bit > - results */ > + /* 32-bit ops (non 64-bit ops and non load/store ops) generate > + 32-bit results. For the result is zero test below, we can > + ignore high bits, but for further optimizations we need to > + record that the high bits contain garbage. */ > + partmask = mask; > if (!(def->flags & (TCG_OPF_CALL_CLOBBER | TCG_OPF_64BIT))) { > - mask &= 0xffffffffu; > + mask |= ~(tcg_target_ulong)0xffffffffu; > + partmask &= 0xffffffffu; > + affected &= 0xffffffffu; > } > > - if (mask == 0) { > + if (partmask == 0) { > assert(nb_oargs == 1); > tcg_opt_gen_movi(s, op_index, gen_args, op, args[0], 0); > args += nb_args; > Reviewed-by: Paolo Bonzini