From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37107) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wnvey-000249-QP for qemu-devel@nongnu.org; Fri, 23 May 2014 16:01:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wnvep-0005A0-Pm for qemu-devel@nongnu.org; Fri, 23 May 2014 16:01:44 -0400 Received: from mail-qg0-x236.google.com ([2607:f8b0:400d:c04::236]:58573) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wnvep-00058J-Hp for qemu-devel@nongnu.org; Fri, 23 May 2014 16:01:35 -0400 Received: by mail-qg0-f54.google.com with SMTP id q108so8795231qgd.27 for ; Fri, 23 May 2014 13:01:34 -0700 (PDT) Sender: Richard Henderson Message-ID: <537FA918.9080006@twiddle.net> Date: Fri, 23 May 2014 13:01:28 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1400871431-12655-1-git-send-email-rth@twiddle.net> <1400871431-12655-3-git-send-email-rth@twiddle.net> <537FA597.3050703@redhat.com> In-Reply-To: <537FA597.3050703@redhat.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 2/2] tcg/optimize: Remember garbage high bits for 32-bit ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org Cc: aurelien@aurel32.net, HPENNER@de.ibm.com On 05/23/2014 12:46 PM, Paolo Bonzini wrote: >> @@ -166,11 +166,18 @@ static void tcg_opt_gen_mov(TCGContext *s, int >> op_index, TCGArg *gen_args, >> TCGOpcode old_op, TCGArg dst, TCGArg src) >> { >> TCGOpcode new_op = op_to_mov(old_op); >> + tcg_target_ulong mask; >> >> s->gen_opc_buf[op_index] = new_op; >> >> reset_temp(dst); >> - temps[dst].mask = temps[src].mask; >> + mask = temps[src].mask; >> + if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) { >> + /* High bits of the destination are now garbage. */ > > Or they are zero on x86_64... perhaps this could be some kind of TCG target hook. Only if we actually issued a "mov" insn. If the register allocator decided to adjust its tables instead, we won't issue an insn, at which point we really do have garbage in the high bits. I don't think we should be thinking about the target at all at this point. r~