From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48964) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoBYS-00041l-GL for qemu-devel@nongnu.org; Sat, 24 May 2014 09:00:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WoBYJ-00059W-Gc for qemu-devel@nongnu.org; Sat, 24 May 2014 09:00:04 -0400 Received: from mail-we0-x233.google.com ([2a00:1450:400c:c03::233]:63105) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoBYJ-00059L-8A for qemu-devel@nongnu.org; Sat, 24 May 2014 08:59:55 -0400 Received: by mail-we0-f179.google.com with SMTP id q59so5943893wes.38 for ; Sat, 24 May 2014 05:59:54 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <538097C4.6000208@redhat.com> Date: Sat, 24 May 2014 14:59:48 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1399041202-26184-1-git-send-email-pbonzini@redhat.com> <1399041202-26184-7-git-send-email-pbonzini@redhat.com> <537F8F32.40305@redhat.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 6/8] cpu: make CPU_INTERRUPT_RESET available on all targets List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers Il 24/05/2014 10:30, Peter Maydell ha scritto: > Well, I'm planning to move the bodies of all the ifdefs into > a cpu_check_interrupts() provided by the target's cpu.h[*]. > This x86 bit is just awkward because it means there's > x86 stuff both before and after the generic reset code. What about if (interrupt_request & CPU_INTERRUPT_DEBUG) { cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG; cpu->exception_index = EXCP_DEBUG; cpu_loop_exit(cpu); } if (!cpu_check_interrupts(...)) { if (interrupt_request & CPU_INTERRUPT_HALT) { cpu->interrupt_request &= ~CPU_INTERRUPT_HALT; cpu->halted = 1; cpu->exception_index = EXCP_HLT; cpu_loop_exit(cpu); } if (interrupt_request & CPU_INTERRUPT_RESET) { cpu_reset(cpu); } } Then: - only X86 returns 1 for CPU_INTERRUPT_RESET - all except ARM/SPARC/MIPS/PPC/Alpha/cris/MicroBlaze/LM32/Unicore32 return 1 for CPU_INTERRUPT_HALT > [*] not a cpu method since it seemed like it would be > a bad idea to have a function pointer call every > time round the main loop when there's a blocked > interrupt... We have that already for cc->do_interrupt, which could be "devirtualized" if you add a check_interrupts method... In the end you'd be adding a function pointer call for all interrupt requests but removing one for CPU_INTERRUPT_HARD (and FIQ too on ARM). That should be a wash. Paolo