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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id x29-20020aa79a5d000000b004f0ef1822d3sm15895320pfj.128.2022.03.20.12.07.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 20 Mar 2022 12:07:49 -0700 (PDT) Message-ID: <5389600e-2bce-3db4-3826-1d46221dddb0@linaro.org> Date: Sun, 20 Mar 2022 12:07:47 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH 1/2] fix cmpxchg instruction Content-Language: en-US To: Wei Li , pbonzini@redhat.com, eduardo@habkost.net References: <20220319160658.336882-1-lw945lw945@yahoo.com> <20220319160658.336882-2-lw945lw945@yahoo.com> From: Richard Henderson In-Reply-To: <20220319160658.336882-2-lw945lw945@yahoo.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::634 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/19/22 09:06, Wei Li wrote: > We need a branch to determine when the instruction can touch the > accumulator. But there is a branch provided by movcond. There is no branch in movcond -- this expands to cmov. > - /* store value = (old == cmp ? new : old); */ > - tcg_gen_movcond_tl(TCG_COND_EQ, newv, oldv, cmpv, newv, oldv); > + tcg_gen_brcond_tl(TCG_COND_EQ, oldv, cmpv, label1); ... > /* Perform an unconditional store cycle like physical cpu; > must be before changing accumulator to ensure > idempotency if the store faults and the instruction > is restarted */ Your branch invalidates the comment -- the store becomes conditional, and we no longer get a write fault on read-only pages when the comparison fails. OTOH, we're already getting the incorrect SIGSEGV behaviour, since we get a read fault on an unmapped page instead of a write fault. The faulting behaviour could be addressed with a write_probe prior to the original load. Alternately, we can use the tcg_gen_atomic_cmpxchg_tl path whenever mod != 3. While an unlocked cmpxchg need not be atomic, it is not required to be non-atomic either, and it would reduce code duplication. r~