From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43019) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wrrhn-00071F-Al for qemu-devel@nongnu.org; Tue, 03 Jun 2014 12:37:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wrrhh-0006aW-Bj for qemu-devel@nongnu.org; Tue, 03 Jun 2014 12:36:55 -0400 Message-ID: <538DF99D.4050805@gmail.com> Date: Tue, 03 Jun 2014 11:36:45 -0500 From: Tom Musta MIME-Version: 1.0 References: <1401787684-31895-1-git-send-email-aik@ozlabs.ru> <1401787684-31895-7-git-send-email-aik@ozlabs.ru> In-Reply-To: <1401787684-31895-7-git-send-email-aik@ozlabs.ru> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 06/29] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Alexander Graf On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote: > MMCR0, MMCR1, MMCRA, PMC1..6, SIAR, SDAR are defined for 970 and PowerISA > CPUs. Since we are building common infrastructure for SPRs intialization > to share it between 970 and POWER5+/7/..., let's add missing SPRs to > the 970 family. Later rework of CPU class initialization will use those > for all PowerISA CPUs. > > Signed-off-by: Alexey Kardashevskiy > --- > target-ppc/translate_init.c | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index f7fe549..e4c9a4c 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -7356,6 +7356,10 @@ static void gen_spr_book3s_pmu_hypv(CPUPPCState *env) > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > 0x00000000); > + spr_register(env, SPR_POWER_MMCRA, "MMCRA", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > spr_register(env, SPR_POWER_PMC1, "PMC1", > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > @@ -7372,10 +7376,22 @@ static void gen_spr_book3s_pmu_hypv(CPUPPCState *env) > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > 0x00000000); > + spr_register(env, SPR_POWER_PMC5, "PMC5", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register(env, SPR_POWER_PMC6, "PMC6", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > spr_register(env, SPR_POWER_SIAR, "SIAR", > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, SPR_NOACCESS, > 0x00000000); > + spr_register(env, SPR_POWER_SDAR, "SDAR", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, SPR_NOACCESS, > + 0x00000000); > } > > static void gen_spr_book3s_pmu_user(CPUPPCState *env) > @@ -7388,6 +7404,10 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env) > &spr_read_ureg, SPR_NOACCESS, > &spr_read_ureg, SPR_NOACCESS, > 0x00000000); > + spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", > + &spr_read_ureg, SPR_NOACCESS, > + &spr_read_ureg, SPR_NOACCESS, > + 0x00000000); > spr_register(env, SPR_POWER_UPMC1, "UPMC1", > &spr_read_ureg, SPR_NOACCESS, > &spr_read_ureg, SPR_NOACCESS, > @@ -7404,10 +7424,22 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env) > &spr_read_ureg, SPR_NOACCESS, > &spr_read_ureg, SPR_NOACCESS, > 0x00000000); > + spr_register(env, SPR_POWER_UPMC5, "UPMC5", > + &spr_read_ureg, SPR_NOACCESS, > + &spr_read_ureg, SPR_NOACCESS, > + 0x00000000); > + spr_register(env, SPR_POWER_UPMC6, "UPMC6", > + &spr_read_ureg, SPR_NOACCESS, > + &spr_read_ureg, SPR_NOACCESS, > + 0x00000000); > spr_register(env, SPR_POWER_USIAR, "USIAR", > &spr_read_ureg, SPR_NOACCESS, > &spr_read_ureg, SPR_NOACCESS, > 0x00000000); > + spr_register(env, SPR_POWER_USDAR, "USDAR", > + &spr_read_ureg, SPR_NOACCESS, > + &spr_read_ureg, SPR_NOACCESS, > + 0x00000000); > } > > static void gen_spr_power5p_ear(CPUPPCState *env) > Similar comments on the Uxxxx SPRs as I made for patch 4. Still OK with addressing this later. Reviewed-by: Tom Musta