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Subject: Re: [Qemu-devel] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR
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To: Alexey Kardashevskiy <aik@ozlabs.ru>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, Alexander Graf <agraf@suse.de>

On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This adds TIR (Thread Identification Register) SPR first defined in
> PowerISA 2.05.
> 
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> Changes:
> v4:
> * disabled reading it from user space
> ---
>  target-ppc/cpu.h            | 1 +
>  target-ppc/translate_init.c | 5 +++++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 97f01ca..8f43b37 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1374,6 +1374,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>  #define SPR_BOOKE_GIVOR8      (0x1BB)
>  #define SPR_BOOKE_GIVOR13     (0x1BC)
>  #define SPR_BOOKE_GIVOR14     (0x1BD)
> +#define SPR_TIR               (0x1BE)
>  #define SPR_BOOKE_SPEFSCR     (0x200)
>  #define SPR_Exxx_BBEAR        (0x201)
>  #define SPR_Exxx_BBTAR        (0x202)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 17163e7..c41d289 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7509,6 +7509,11 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
>                   SPR_NOACCESS, SPR_NOACCESS,
>                   &spr_read_generic, &spr_write_pir,
>                   0x00000000);
> +
> +    spr_register(env, SPR_TIR, "TIR",
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 &spr_read_generic, SPR_NOACCESS,
> +                 0x00000000);
>  }
>  
>  static void gen_spr_book3s_purr(CPUPPCState *env)
> 

It looks like TIR gets added to both P7 and P8.  Intentional?  (TIR was added in ISA 2.07 ... not sure if it existed in P7 implementations or not).