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From: Tom Musta <tommusta@gmail.com>
To: Alexey Kardashevskiy <aik@ozlabs.ru>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, Alexander Graf <agraf@suse.de>
Subject: Re: [Qemu-devel] [PATCH v4 22/29] target-ppc: Add POWER8's MMCR2/MMCRS SPRs
Date: Tue, 03 Jun 2014 12:10:41 -0500	[thread overview]
Message-ID: <538E0191.9020607@gmail.com> (raw)
In-Reply-To: <1401787684-31895-23-git-send-email-aik@ozlabs.ru>

On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This adds POWER8 specific PMU MMCR2/MMCRS SPRs.
> 
> This adds a spr_write_ureg helper for changing a hypv-privileged SPR when
> it is accessed via its user-privileged mirror. A spr_read_ureg() is
> already there. Since the new helper is only used by book3s CPUs, it is
> limited to TARGET_PPC64 to make gcc happy when QEMU is compiled for 32 bit.
> 
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> Changes:
> v4:
> * disabled write_ureg for user mode, privileged mode is still needed for
> recent guest kernels to boot on POWER8
> ---
>  target-ppc/cpu.h            |  3 +++
>  target-ppc/translate_init.c | 29 +++++++++++++++++++++++++++++
>  2 files changed, 32 insertions(+)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 32fadcd..cf1ccad 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1480,6 +1480,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>  #define SPR_MPC_MI_CTR        (0x300)
>  #define SPR_PERF1             (0x301)
>  #define SPR_RCPU_MI_RBA1      (0x301)
> +#define SPR_POWER_UMMCR2      (0x301)
>  #define SPR_PERF2             (0x302)
>  #define SPR_RCPU_MI_RBA2      (0x302)
>  #define SPR_MPC_MI_AP         (0x302)
> @@ -1527,6 +1528,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>  #define SPR_MPC_MD_TW         (0x30F)
>  #define SPR_UPERF0            (0x310)
>  #define SPR_UPERF1            (0x311)
> +#define SPR_POWER_MMCR2       (0x311)
>  #define SPR_UPERF2            (0x312)
>  #define SPR_POWER_MMCRA       (0X312)
>  #define SPR_UPERF3            (0x313)
> @@ -1579,6 +1581,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>  #define SPR_440_ITV3          (0x377)
>  #define SPR_440_CCR1          (0x378)
>  #define SPR_DCRIPR            (0x37B)
> +#define SPR_POWER_MMCRS       (0x37E)
>  #define SPR_PPR               (0x380)
>  #define SPR_750_GQR0          (0x390)
>  #define SPR_440_DNV0          (0x390)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 9b83d56..6bb0788 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -175,6 +175,13 @@ static void spr_read_ureg (void *opaque, int gprn, int sprn)
>      gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
>  }
>  
> +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> +static void spr_write_ureg(void *opaque, int sprn, int gprn)
> +{
> +    gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
> +}
> +#endif
> +
>  /* SPR common to all non-embedded PowerPC */
>  /* DECR */
>  #if !defined(CONFIG_USER_ONLY)
> @@ -7500,6 +7507,26 @@ static void gen_spr_970_pmu_user(CPUPPCState *env)
>                   0x00000000);
>  }
>  
> +static void gen_spr_power8_pmu_hypv(CPUPPCState *env)
> +{
> +    spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
> +                     SPR_NOACCESS, SPR_NOACCESS,
> +                     &spr_read_generic, &spr_write_generic,
> +                     KVM_REG_PPC_MMCR2, 0x00000000);
> +    spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
> +                     SPR_NOACCESS, SPR_NOACCESS,
> +                     &spr_read_generic, &spr_write_generic,
> +                     KVM_REG_PPC_MMCRS, 0x00000000);
> +}


Supervisor.

> +
> +static void gen_spr_power8_pmu_user(CPUPPCState *env)
> +{
> +    spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
> +                 &spr_read_ureg, SPR_NOACCESS,
> +                 &spr_read_ureg, &spr_write_ureg,
> +                 0x00000000);
> +}
> +

The write_ureg should probably also be applied to the other PMU Uxxxx SPRs, no?

>  static void gen_spr_power5p_ear(CPUPPCState *env)
>  {
>      /* External access control */
> @@ -7656,6 +7683,8 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>      if (version >= BOOK3S_CPU_POWER8) {
>          gen_spr_power8_tce_address_control(env);
>          gen_spr_power8_fscr(env);
> +        gen_spr_power8_pmu_hypv(env);
> +        gen_spr_power8_pmu_user(env);
>      }
>  #if !defined(CONFIG_USER_ONLY)
>      switch (version) {
> 

Reviewed-by: Tom Musta <tommusta@gmail.com>

  reply	other threads:[~2014-06-03 17:10 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-03  9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 01/29] target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs Alexey Kardashevskiy
2014-06-03 16:32   ` Tom Musta
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class Alexey Kardashevskiy
2014-06-03 15:40   ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2014-06-03 16:11     ` Alexander Graf
2014-06-03 16:25   ` [Qemu-devel] " Tom Musta
2014-06-04  4:48     ` Alexey Kardashevskiy
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 03/29] target-ppc: Refactor PPC970 Alexey Kardashevskiy
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 04/29] target-ppc: Copy and split gen_spr_7xx() for 970 Alexey Kardashevskiy
2014-06-03 16:32   ` Tom Musta
2014-06-04  5:09     ` Alexey Kardashevskiy
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 05/29] target-ppc: Add "POWER" prefix to MMCRA PMU registers Alexey Kardashevskiy
2014-06-03 16:35   ` Tom Musta
2014-06-04  1:36     ` Alexey Kardashevskiy
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 06/29] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family Alexey Kardashevskiy
2014-06-03 16:36   ` Tom Musta
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 07/29] target-ppc: Add PMC7/8 to 970 class Alexey Kardashevskiy
2014-06-03 16:37   ` Tom Musta
2014-06-03 16:42   ` Tom Musta
2014-06-04  5:25     ` Alexey Kardashevskiy
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 08/29] target-ppc: Add HID4 SPR for PPC970 Alexey Kardashevskiy
2014-06-03 16:43   ` Tom Musta
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 09/29] target-ppc: Introduce and reuse generalized init_proc_book3s_64() Alexey Kardashevskiy
2014-06-03 16:45   ` Tom Musta
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 10/29] target-ppc: Remove check_pow_970FX Alexey Kardashevskiy
2014-06-03 16:45   ` Tom Musta
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 11/29] target-ppc: Enable PMU SPRs migration Alexey Kardashevskiy
2014-06-03 16:47   ` Tom Musta
2014-06-04  1:46     ` Alexey Kardashevskiy
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 12/29] target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers Alexey Kardashevskiy
2014-06-03 16:48   ` Tom Musta
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 13/29] target-ppc: Move POWER8 TCE Address control (TAR) to a helper Alexey Kardashevskiy
2014-06-03 16:48   ` Tom Musta
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 14/29] target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers Alexey Kardashevskiy
2014-06-03 16:54   ` Tom Musta
2014-06-04  2:02     ` Alexey Kardashevskiy
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 15/29] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8 Alexey Kardashevskiy
2014-06-03 16:54   ` Tom Musta
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 16/29] target-ppc: Make use of gen_spr_book3s_lpar() " Alexey Kardashevskiy
2014-06-03 16:54   ` Tom Musta
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 17/29] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs Alexey Kardashevskiy
2014-06-03 16:55   ` Tom Musta
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 18/29] target-ppc: Refactor class init for POWER7/8 Alexey Kardashevskiy
2014-06-03 16:57   ` Tom Musta
2014-06-04  2:09     ` Alexey Kardashevskiy
2014-06-04 12:24       ` Tom Musta
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR Alexey Kardashevskiy
2014-06-03 16:59   ` Tom Musta
2014-06-04  2:14     ` Alexey Kardashevskiy
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 20/29] target-ppc: Add POWER8's FSCR SPR Alexey Kardashevskiy
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR Alexey Kardashevskiy
2014-06-03 17:08   ` Tom Musta
2014-06-04  2:37     ` Alexey Kardashevskiy
2014-06-04 12:25       ` Tom Musta
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 22/29] target-ppc: Add POWER8's MMCR2/MMCRS SPRs Alexey Kardashevskiy
2014-06-03 17:10   ` Tom Musta [this message]
2014-06-03 23:42     ` Alexey Kardashevskiy
2014-06-04  5:26       ` Alexey Kardashevskiy
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 23/29] target-ppc: Add POWER8's TM SPRs Alexey Kardashevskiy
2014-06-03 17:58   ` Tom Musta
2014-06-04  2:54     ` Alexey Kardashevskiy
2014-06-04 12:30       ` Tom Musta
2014-06-03  9:27 ` [Qemu-devel] [PATCH v4 24/29] KVM: target-ppc: Enable TM state migration Alexey Kardashevskiy
2014-06-03  9:28 ` [Qemu-devel] [PATCH v4 25/29] target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs Alexey Kardashevskiy
2014-06-03 18:01   ` Tom Musta
2014-06-03  9:28 ` [Qemu-devel] [PATCH v4 26/29] target-ppc: Enable PPR and VRSAVE SPRs migration Alexey Kardashevskiy
2014-06-03  9:28 ` [Qemu-devel] [PATCH v4 27/29] target-ppc: Enable DABRX SPR and limit it to <=POWER7 Alexey Kardashevskiy
2014-06-03 18:05   ` Tom Musta
2014-06-04  3:12     ` Alexey Kardashevskiy
2014-06-03  9:28 ` [Qemu-devel] [PATCH v4 28/29] spapr_hcall: Split h_set_mode() Alexey Kardashevskiy
2014-06-03  9:28 ` [Qemu-devel] [PATCH v4 29/29] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE Alexey Kardashevskiy
2014-06-03 16:51   ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2014-06-03 23:44     ` Alexey Kardashevskiy

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