From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52113) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WrsEd-0005v8-D8 for qemu-devel@nongnu.org; Tue, 03 Jun 2014 13:10:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WrsEX-0003QF-5Z for qemu-devel@nongnu.org; Tue, 03 Jun 2014 13:10:51 -0400 Message-ID: <538E0191.9020607@gmail.com> Date: Tue, 03 Jun 2014 12:10:41 -0500 From: Tom Musta MIME-Version: 1.0 References: <1401787684-31895-1-git-send-email-aik@ozlabs.ru> <1401787684-31895-23-git-send-email-aik@ozlabs.ru> In-Reply-To: <1401787684-31895-23-git-send-email-aik@ozlabs.ru> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 22/29] target-ppc: Add POWER8's MMCR2/MMCRS SPRs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Alexander Graf On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote: > This adds POWER8 specific PMU MMCR2/MMCRS SPRs. > > This adds a spr_write_ureg helper for changing a hypv-privileged SPR when > it is accessed via its user-privileged mirror. A spr_read_ureg() is > already there. Since the new helper is only used by book3s CPUs, it is > limited to TARGET_PPC64 to make gcc happy when QEMU is compiled for 32 bit. > > Signed-off-by: Alexey Kardashevskiy > --- > Changes: > v4: > * disabled write_ureg for user mode, privileged mode is still needed for > recent guest kernels to boot on POWER8 > --- > target-ppc/cpu.h | 3 +++ > target-ppc/translate_init.c | 29 +++++++++++++++++++++++++++++ > 2 files changed, 32 insertions(+) > > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index 32fadcd..cf1ccad 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -1480,6 +1480,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) > #define SPR_MPC_MI_CTR (0x300) > #define SPR_PERF1 (0x301) > #define SPR_RCPU_MI_RBA1 (0x301) > +#define SPR_POWER_UMMCR2 (0x301) > #define SPR_PERF2 (0x302) > #define SPR_RCPU_MI_RBA2 (0x302) > #define SPR_MPC_MI_AP (0x302) > @@ -1527,6 +1528,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) > #define SPR_MPC_MD_TW (0x30F) > #define SPR_UPERF0 (0x310) > #define SPR_UPERF1 (0x311) > +#define SPR_POWER_MMCR2 (0x311) > #define SPR_UPERF2 (0x312) > #define SPR_POWER_MMCRA (0X312) > #define SPR_UPERF3 (0x313) > @@ -1579,6 +1581,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) > #define SPR_440_ITV3 (0x377) > #define SPR_440_CCR1 (0x378) > #define SPR_DCRIPR (0x37B) > +#define SPR_POWER_MMCRS (0x37E) > #define SPR_PPR (0x380) > #define SPR_750_GQR0 (0x390) > #define SPR_440_DNV0 (0x390) > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 9b83d56..6bb0788 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -175,6 +175,13 @@ static void spr_read_ureg (void *opaque, int gprn, int sprn) > gen_load_spr(cpu_gpr[gprn], sprn + 0x10); > } > > +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) > +static void spr_write_ureg(void *opaque, int sprn, int gprn) > +{ > + gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); > +} > +#endif > + > /* SPR common to all non-embedded PowerPC */ > /* DECR */ > #if !defined(CONFIG_USER_ONLY) > @@ -7500,6 +7507,26 @@ static void gen_spr_970_pmu_user(CPUPPCState *env) > 0x00000000); > } > > +static void gen_spr_power8_pmu_hypv(CPUPPCState *env) > +{ > + spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + KVM_REG_PPC_MMCR2, 0x00000000); > + spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + KVM_REG_PPC_MMCRS, 0x00000000); > +} Supervisor. > + > +static void gen_spr_power8_pmu_user(CPUPPCState *env) > +{ > + spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", > + &spr_read_ureg, SPR_NOACCESS, > + &spr_read_ureg, &spr_write_ureg, > + 0x00000000); > +} > + The write_ureg should probably also be applied to the other PMU Uxxxx SPRs, no? > static void gen_spr_power5p_ear(CPUPPCState *env) > { > /* External access control */ > @@ -7656,6 +7683,8 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) > if (version >= BOOK3S_CPU_POWER8) { > gen_spr_power8_tce_address_control(env); > gen_spr_power8_fscr(env); > + gen_spr_power8_pmu_hypv(env); > + gen_spr_power8_pmu_user(env); > } > #if !defined(CONFIG_USER_ONLY) > switch (version) { > Reviewed-by: Tom Musta