From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38095) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wrt1u-0005Xw-4U for qemu-devel@nongnu.org; Tue, 03 Jun 2014 14:01:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wrt1o-0005yl-59 for qemu-devel@nongnu.org; Tue, 03 Jun 2014 14:01:46 -0400 Message-ID: <538E0D7F.8020908@gmail.com> Date: Tue, 03 Jun 2014 13:01:35 -0500 From: Tom Musta MIME-Version: 1.0 References: <1401787684-31895-1-git-send-email-aik@ozlabs.ru> <1401787684-31895-26-git-send-email-aik@ozlabs.ru> In-Reply-To: <1401787684-31895-26-git-send-email-aik@ozlabs.ru> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 25/29] target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Alexander Graf On 6/3/2014 4:28 AM, Alexey Kardashevskiy wrote: > POWER8 supports Event-Based Branch Facility (EBB). It is controlled via > set of SPRs access to which should generate an "Facility Unavailable" > interrupt if the facilities are not enabled in FSCR for problem state. > > This adds EBB SPRs. > > Signed-off-by: Alexey Kardashevskiy > --- > target-ppc/cpu.h | 7 ++++++ > target-ppc/translate_init.c | 57 +++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 64 insertions(+) > > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index 318b32a..e33828a 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -1582,11 +1582,18 @@ static inline int cpu_mmu_index (CPUPPCState *env) > #define SPR_UPERFF (0x31F) > #define SPR_RCPU_MI_RA0 (0x320) > #define SPR_MPC_MI_DBCAM (0x320) > +#define SPR_BESCRS (0x320) > #define SPR_RCPU_MI_RA1 (0x321) > #define SPR_MPC_MI_DBRAM0 (0x321) > +#define SPR_BESCRSU (0x321) > #define SPR_RCPU_MI_RA2 (0x322) > #define SPR_MPC_MI_DBRAM1 (0x322) > +#define SPR_BESCRR (0x322) > #define SPR_RCPU_MI_RA3 (0x323) > +#define SPR_BESCRRU (0x323) > +#define SPR_EBBHR (0x324) > +#define SPR_EBBRR (0x325) > +#define SPR_BESCR (0x326) > #define SPR_RCPU_L2U_RA0 (0x328) > #define SPR_MPC_MD_DBCAM (0x328) > #define SPR_RCPU_L2U_RA1 (0x329) > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index bb4201c..ab40f9e 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -7713,6 +7713,62 @@ static void gen_spr_power8_tm(CPUPPCState *env) > 0x00000000); > } > > +static void spr_read_ebb(void *opaque, int gprn, int sprn) > +{ > + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); > + spr_read_generic(opaque, gprn, sprn); > +} > + > +static void spr_write_ebb(void *opaque, int sprn, int gprn) > +{ > + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); > + spr_write_generic(opaque, sprn, gprn); > +} > + > +static void spr_read_ebb_upper32(void *opaque, int gprn, int sprn) > +{ > + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); > + spr_read_prev_upper32(opaque, gprn, sprn); > +} > + > +static void spr_write_ebb_upper32(void *opaque, int sprn, int gprn) > +{ > + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); > + spr_write_prev_upper32(opaque, sprn, gprn); > +} > + > +static void gen_spr_power8_ebb(CPUPPCState *env) > +{ > + spr_register(env, SPR_BESCRS, "BESCRS", > + &spr_read_ebb, &spr_write_ebb, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register(env, SPR_BESCRSU, "BESCRSU", > + &spr_read_ebb_upper32, &spr_write_ebb_upper32, > + &spr_read_prev_upper32, &spr_write_prev_upper32, > + 0x00000000); > + spr_register(env, SPR_BESCRR, "BESCRR", > + &spr_read_ebb, &spr_write_ebb, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register(env, SPR_BESCRRU, "BESCRRU", > + &spr_read_ebb_upper32, &spr_write_ebb_upper32, > + &spr_read_prev_upper32, &spr_write_prev_upper32, > + 0x00000000); > + spr_register_kvm(env, SPR_EBBHR, "EBBHR", > + &spr_read_ebb, &spr_write_ebb, > + &spr_read_generic, &spr_write_generic, > + KVM_REG_PPC_EBBHR, 0x00000000); > + spr_register_kvm(env, SPR_EBBRR, "EBBRR", > + &spr_read_ebb, &spr_write_ebb, > + &spr_read_generic, &spr_write_generic, > + KVM_REG_PPC_EBBRR, 0x00000000); > + spr_register_kvm(env, SPR_BESCR, "BESCR", > + &spr_read_ebb, &spr_write_ebb, > + &spr_read_generic, &spr_write_generic, > + KVM_REG_PPC_BESCR, 0x00000000); > +} > + > static void gen_spr_power8_fscr(CPUPPCState *env) > { > spr_register_kvm(env, SPR_FSCR, "FSCR", > @@ -7765,6 +7821,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) > } > if (version >= BOOK3S_CPU_POWER8) { > gen_spr_power8_tce_address_control(env); > + gen_spr_power8_ebb(env); > gen_spr_power8_fscr(env); > gen_spr_power8_pmu_hypv(env); > gen_spr_power8_pmu_user(env); > Reviewed-by: Tom Musta