From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46408) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ws0dy-0002Lc-Ro for qemu-devel@nongnu.org; Tue, 03 Jun 2014 22:09:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ws0ds-00013V-JX for qemu-devel@nongnu.org; Tue, 03 Jun 2014 22:09:34 -0400 Received: from mail-pb0-f43.google.com ([209.85.160.43]:58965) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ws0ds-00012a-El for qemu-devel@nongnu.org; Tue, 03 Jun 2014 22:09:28 -0400 Received: by mail-pb0-f43.google.com with SMTP id up15so6296955pbc.30 for ; Tue, 03 Jun 2014 19:09:27 -0700 (PDT) Message-ID: <538E7FD3.4090303@ozlabs.ru> Date: Wed, 04 Jun 2014 12:09:23 +1000 From: Alexey Kardashevskiy MIME-Version: 1.0 References: <1401787684-31895-1-git-send-email-aik@ozlabs.ru> <1401787684-31895-19-git-send-email-aik@ozlabs.ru> <538DFE7B.5010606@gmail.com> In-Reply-To: <538DFE7B.5010606@gmail.com> Content-Type: text/plain; charset=KOI8-R Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 18/29] target-ppc: Refactor class init for POWER7/8 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tom Musta , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Alexander Graf On 06/04/2014 02:57 AM, Tom Musta wrote: > On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote: >> This extends init_proc_book3s_64 to support POWER7 and POWER8. >> >> Signed-off-by: Alexey Kardashevskiy >> --- >> Changes: >> v4: >> * added g_assert_not_reached() to default path to catch errors earlier >> --- >> target-ppc/translate_init.c | 100 +++++++++++++++++++++++++++----------------- >> 1 file changed, 61 insertions(+), 39 deletions(-) >> >> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c >> index b1288f4..17163e7 100644 >> --- a/target-ppc/translate_init.c >> +++ b/target-ppc/translate_init.c >> @@ -7269,6 +7269,9 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) >> enum BOOK3S_CPU_TYPE { >> BOOK3S_CPU_970, >> BOOK3S_CPU_POWER5PLUS, >> + BOOK3S_CPU_POWER6, >> + BOOK3S_CPU_POWER7, >> + BOOK3S_CPU_POWER8 >> }; >> >> static int check_pow_970 (CPUPPCState *env) >> @@ -7575,30 +7578,74 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) >> gen_spr_book3s_pmu_hypv(env); >> gen_spr_book3s_pmu_user(env); >> gen_spr_book3s_dbg(env); >> - >> - gen_spr_970_hid(env); >> - gen_spr_970_hior(env); >> - gen_low_BATs(env); >> gen_spr_book3s_common(env); >> - gen_spr_970_pmu_hypv(env); >> - gen_spr_970_pmu_user(env); >> >> + switch (version) { >> + case BOOK3S_CPU_970: >> + case BOOK3S_CPU_POWER5PLUS: >> + gen_spr_970_hid(env); >> + gen_spr_970_hior(env); >> + gen_low_BATs(env); >> + gen_spr_970_pmu_hypv(env); >> + gen_spr_970_pmu_user(env); >> + break; > > > It appears the 970/P5+ models now have both the old and the new PMU SPR numbers .... intentional? How so? gen_spr_book3s_pmu_xxx add PCM1..6, gen_spr_970_pmu_xxx add PMC7-8. Since patch #4, 970/p5+ do not use old PMU SPRs. -- Alexey