From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55319) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ws3hS-0002St-8n for qemu-devel@nongnu.org; Wed, 04 Jun 2014 01:25:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ws3hM-0002m0-10 for qemu-devel@nongnu.org; Wed, 04 Jun 2014 01:25:22 -0400 Received: from mail-pb0-f48.google.com ([209.85.160.48]:50979) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ws3hL-0002lr-Rk for qemu-devel@nongnu.org; Wed, 04 Jun 2014 01:25:15 -0400 Received: by mail-pb0-f48.google.com with SMTP id rr13so6491814pbb.21 for ; Tue, 03 Jun 2014 22:25:14 -0700 (PDT) Message-ID: <538EADB5.6040804@ozlabs.ru> Date: Wed, 04 Jun 2014 15:25:09 +1000 From: Alexey Kardashevskiy MIME-Version: 1.0 References: <1401787684-31895-1-git-send-email-aik@ozlabs.ru> <1401787684-31895-8-git-send-email-aik@ozlabs.ru> <538DFAF3.2070106@gmail.com> In-Reply-To: <538DFAF3.2070106@gmail.com> Content-Type: text/plain; charset=KOI8-R Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 07/29] target-ppc: Add PMC7/8 to 970 class List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tom Musta , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Alexander Graf On 06/04/2014 02:42 AM, Tom Musta wrote: > On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote: >> Compared to PowerISA-compliant CPUs, 970 family has most of them plus >> PMC7/8 which are only present on 970 but not on POWER5 and later CPUs. >> >> Since we are changing SPRs for Book3s/970 families, let's add them too. >> >> Signed-off-by: Alexey Kardashevskiy >> --- >> target-ppc/cpu.h | 4 ++++ >> target-ppc/translate_init.c | 26 ++++++++++++++++++++++++++ >> 2 files changed, 30 insertions(+) >> > > [ ... ] > >> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c >> index e4c9a4c..0fcf918 100644 >> --- a/target-ppc/translate_init.c >> +++ b/target-ppc/translate_init.c >> @@ -7442,6 +7442,30 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env) >> 0x00000000); >> } >> >> +static void gen_spr_970_pmu_hypv(CPUPPCState *env) >> +{ >> + spr_register(env, SPR_970_PMC7, "PMC7", >> + SPR_NOACCESS, SPR_NOACCESS, >> + &spr_read_generic, &spr_write_generic, >> + 0x00000000); >> + spr_register(env, SPR_970_PMC8, "PMC8", >> + SPR_NOACCESS, SPR_NOACCESS, >> + &spr_read_generic, &spr_write_generic, >> + 0x00000000); >> +} >> + > > Sorry ... forgot my comments: Shouldn't this be named "gen_spr_970_pm_sup" ? These are supervisor SPRs, not hypervisor SPRs. Will be fixed in v5. >> +static void gen_spr_970_pmu_user(CPUPPCState *env) >> +{ >> + spr_register(env, SPR_970_UPMC7, "UPMC7", >> + &spr_read_ureg, SPR_NOACCESS, >> + &spr_read_ureg, SPR_NOACCESS, >> + 0x00000000); >> + spr_register(env, SPR_970_UPMC8, "UPMC8", >> + &spr_read_ureg, SPR_NOACCESS, >> + &spr_read_ureg, SPR_NOACCESS, >> + 0x00000000); >> +} >> + > > Are UPMC7/8 writeable from supervisor state? (the 970 UM is not crystal clear here). No idea either. I suggest enabling writes there and get back to the topic when/if we decide to model them correctly. Ok? -- Alexey