From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:50601)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1WsItc-0003TF-Po
	for qemu-devel@nongnu.org; Wed, 04 Jun 2014 17:39:05 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1WsItT-0000AQ-Oi
	for qemu-devel@nongnu.org; Wed, 04 Jun 2014 17:38:56 -0400
Sender: Richard Henderson <rth7680@gmail.com>
Message-ID: <538F91D1.1030604@twiddle.net>
Date: Wed, 04 Jun 2014 14:38:25 -0700
From: Richard Henderson <rth@twiddle.net>
MIME-Version: 1.0
References: <1401916152-27169-1-git-send-email-agraf@suse.de>
	<1401916152-27169-2-git-send-email-agraf@suse.de>
In-Reply-To: <1401916152-27169-2-git-send-email-agraf@suse.de>
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH 2/2] PPC: e500: Merge 32 and 64 bit SPE
	emulation
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Alexander Graf <agraf@suse.de>, qemu-ppc@nongnu.org
Cc: Tom Musta <tommusta@gmail.com>, qemu-devel@nongnu.org

On 06/04/2014 02:09 PM, Alexander Graf wrote:
> @@ -9030,13 +8820,10 @@ static inline void gen_evmwumi(DisasContext *ctx)
>      t1 = tcg_temp_new_i64();
>  
>      /* t0 := rA; t1 := rB */
> -#if defined(TARGET_PPC64)
> -    tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
> -    tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
> -#else
>      tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
> +    tcg_gen_ext32u_i64(t0, t0);

Better in one step:

 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);

> @@ -9112,13 +8899,10 @@ static inline void gen_evmwsmi(DisasContext *ctx)
>      t1 = tcg_temp_new_i64();
>  
>      /* t0 := rA; t1 := rB */
> +    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
> +    tcg_gen_ext32s_i64(t0, t0);
> +    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
> +    tcg_gen_ext32s_i64(t1, t1);

Similarly.

Although I do wonder about using the actual 32-bit widening multiply
primitives: tcg_gen_mulu2_i32 / tcg_gen_muls2_i32.

I suspect the optimizer would clean up the unsigned version, but it hasn't got
a chance with the signed version.

Otherwise, it looks ok.



r~