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From: Sergey Fedorov <serge.fdrv@gmail.com>
To: Greg Bellows <greg.bellows@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Peter Crosthwaite <peter.crosthwaite@xilinx.com>,
	Fabian Aggeler <aggelerf@ethz.ch>,
	QEMU Developers <qemu-devel@nongnu.org>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	Christoffer Dall <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v3 04/32] target-arm: add arm_is_secure() function
Date: Thu, 12 Jun 2014 21:26:47 +0400	[thread overview]
Message-ID: <5399E2D7.1060606@gmail.com> (raw)
In-Reply-To: <CAOgzsHUFyashO2XgMJPqL55YU08j2WrWbzrsv+ALi243wU9s5w@mail.gmail.com>

[-- Attachment #1: Type: text/plain, Size: 3175 bytes --]

Hi Greg,

I'm sorry, I wasn't thoughtful enough and missed that.
I would just suggest to combine that functions since they have a common
part, i.e.:

    if (arm_feature(env, ARM_FEATURE_EL3)) {
        ...

What do you think?

// Sergey

12.06.2014 20:26, Greg Bellows пишет:
> Hi Sergey,
>
> I think I am missing your point.  In patch 6 arm_current_pl calls
> arm_is_secure.  Can you elaborate?
>
> Greg
>
>
> On 11 June 2014 07:17, Sergey Fedorov <serge.fdrv@gmail.com
> <mailto:serge.fdrv@gmail.com>> wrote:
>
>     On 11.06.2014 03:54, Fabian Aggeler wrote:
>     > arm_is_secure() function allows to determine CPU security state
>     > if the CPU implements Security Extensions/EL3.
>     > arm_is_secure_below_el3() returns true if CPU is in secure state
>     > below EL3.
>     >
>     > Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com
>     <mailto:s.fedorov@samsung.com>>
>     > Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch
>     <mailto:aggelerf@ethz.ch>>
>     > ---
>     >  target-arm/cpu.h | 38 ++++++++++++++++++++++++++++++++++++++
>     >  1 file changed, 38 insertions(+)
>     >
>     > diff --git a/target-arm/cpu.h b/target-arm/cpu.h
>     > index 903aa01..cb0da6b 100644
>     > --- a/target-arm/cpu.h
>     > +++ b/target-arm/cpu.h
>     > @@ -710,6 +710,44 @@ static inline int arm_feature(CPUARMState
>     *env, int feature)
>     >      return (env->features & (1ULL << feature)) != 0;
>     >  }
>     >
>     > +
>     > +/* Return true if exception level below EL3 is in secure state */
>     > +static inline bool arm_is_secure_below_el3(CPUARMState *env)
>     > +{
>     > +#if !defined(CONFIG_USER_ONLY)
>     > +    if (arm_feature(env, ARM_FEATURE_EL3)) {
>     > +        return !(env->cp15.scr_el3 & SCR_NS);
>     > +    } else if (arm_feature(env, ARM_FEATURE_EL2)) {
>     > +        return false;
>     > +    } else {
>     > +        /* IMPDEF: QEMU defaults to non-secure */
>     > +        return false;
>     > +    }
>     > +#else
>     > +    return false;
>     > +#endif
>     > +}
>     > +
>     > +/* Return true if the processor is in secure state */
>     > +static inline bool arm_is_secure(CPUARMState *env)
>     > +{
>     > +#if !defined(CONFIG_USER_ONLY)
>     > +    if (arm_feature(env, ARM_FEATURE_EL3)) {
>     > +        if (env->aarch64 && extract32(env->pstate, 2, 2) == 3) {
>     > +            /* CPU currently in Aarch64 state and EL3 */
>     > +            return true;
>     > +        } else if (!env->aarch64 &&
>     > +                (env->uncached_cpsr & CPSR_M) ==
>     ARM_CPU_MODE_MON) {
>     > +            /* CPU currently in Aarch32 state and monitor mode */
>     > +            return true;
>     > +        }
>
>     Hi Fabian,
>
>     Why don't use arm_current_pl() from patch 6 to determine EL here?
>
>     Best regards,
>     Sergey
>
>     > +    }
>     > +    return arm_is_secure_below_el3(env);
>     > +#else
>     > +    return false;
>     > +#endif
>     > +}
>     > +
>     >  /* Return true if the specified exception level is running in
>     AArch64 state. */
>     >  static inline bool arm_el_is_aa64(CPUARMState *env, int el)
>     >  {
>
>


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  reply	other threads:[~2014-06-12 17:27 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-10 23:54 [Qemu-devel] [PATCH v3 00/32] target-arm: add Security Extensions for CPUs Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 01/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 02/32] target-arm: move Aarch32 SCR into security reglist Fabian Aggeler
2014-06-12 21:55   ` Greg Bellows
2014-06-17  7:22     ` Aggeler  Fabian
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 03/32] target-arm: increase arrays of registers R13 & R14 Fabian Aggeler
2014-06-17  8:57   ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 04/32] target-arm: add arm_is_secure() function Fabian Aggeler
2014-06-11 12:17   ` Sergey Fedorov
2014-06-12 16:26     ` Greg Bellows
2014-06-12 17:26       ` Sergey Fedorov [this message]
2014-06-12 18:35         ` Greg Bellows
2014-06-12 19:09           ` Sergey Fedorov
2014-06-17  5:51   ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 05/32] target-arm: reject switching to monitor mode Fabian Aggeler
2014-06-12 21:55   ` Greg Bellows
2014-06-24 12:19     ` Aggeler  Fabian
2014-06-24 13:43       ` Greg Bellows
2014-06-17  5:43   ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 06/32] target-arm: make arm_current_pl() return PL3 Fabian Aggeler
2014-06-17  5:40   ` Edgar E. Iglesias
2014-06-17  7:12     ` Aggeler  Fabian
2014-06-17  7:07       ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 07/32] target-arm: add non-secure Translation Block flag Fabian Aggeler
2014-06-17  9:15   ` Edgar E. Iglesias
2014-06-17 10:07     ` Sergey Fedorov
2014-06-19  5:30       ` Edgar E. Iglesias
2014-06-25  4:15   ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 08/32] target-arm: A32: Emulate the SMC instruction Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 09/32] target-arm: extend Aarch32 async excp masking Fabian Aggeler
2014-06-17  7:48   ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 10/32] target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling Fabian Aggeler
2014-06-12 21:55   ` Greg Bellows
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 11/32] target-arm: add async excp target_el&mode function Fabian Aggeler
2014-06-12 21:56   ` Greg Bellows
2014-06-17  7:29     ` Aggeler  Fabian
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 12/32] target-arm: use dedicated target_el function Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 13/32] target-arm: implement IRQ/FIQ routing to Monitor mode Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 14/32] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI Fabian Aggeler
2014-06-12 22:43   ` Greg Bellows
2014-06-17  7:36     ` Aggeler  Fabian
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 15/32] target-arm: add NSACR register Fabian Aggeler
2014-06-13 18:27   ` Greg Bellows
2014-06-17  7:41     ` Aggeler  Fabian
2014-06-24 15:37       ` Greg Bellows
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 16/32] target-arm: add SDER definition Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 17/32] target-arm: add MVBAR support Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 18/32] target-arm: add macros to access banked registers Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 19/32] target-arm: insert Aarch32 cpregs twice into hashtable Fabian Aggeler
2014-06-12 19:49   ` Sergey Fedorov
2014-06-25  5:20   ` Edgar E. Iglesias
2014-06-25 13:50     ` Greg Bellows
2014-06-26  3:56       ` Edgar E. Iglesias
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 20/32] target-arm: arrayfying fieldoffset for banking Fabian Aggeler
2014-06-13 20:18   ` Greg Bellows
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 21/32] target-arm: add SCTLR_EL3 and make SCTLR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 22/32] target-arm: make CSSELR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 23/32] target-arm: add TTBR0_EL3 and make TTBR0/1 banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 24/32] target-arm: add TCR_EL3 and make TTBCR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 25/32] target-arm: make c2_mask and c2_base_mask banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 26/32] target-arm: make DACR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 27/32] target-arm: make IFSR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 28/32] target-arm: make DFSR banked Fabian Aggeler
2014-06-13 22:06   ` Greg Bellows
2014-06-17  6:12     ` Edgar E. Iglesias
2014-06-23 16:53       ` Greg Bellows
2014-06-24 11:05       ` Aggeler  Fabian
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 29/32] target-arm: make IFAR/DFAR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 30/32] target-arm: make PAR banked Fabian Aggeler
2014-06-13 22:49   ` Greg Bellows
2014-06-17  7:15     ` Aggeler  Fabian
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 31/32] target-arm: make VBAR banked Fabian Aggeler
2014-06-13 22:43   ` Greg Bellows
2014-06-17  7:17     ` Aggeler  Fabian
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 32/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) Fabian Aggeler
2014-06-23 21:40   ` Greg Bellows
2014-06-24 11:08     ` Aggeler  Fabian
2014-06-11  1:31 ` [Qemu-devel] [PATCH v3 00/32] target-arm: add Security Extensions for CPUs Edgar E. Iglesias

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