From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51050) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WwUvC-0004f6-Sl for qemu-devel@nongnu.org; Mon, 16 Jun 2014 07:18:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WwUv6-0007IF-QU for qemu-devel@nongnu.org; Mon, 16 Jun 2014 07:17:54 -0400 Received: from cantor2.suse.de ([195.135.220.15]:36367 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WwUv6-0007IB-KS for qemu-devel@nongnu.org; Mon, 16 Jun 2014 07:17:48 -0400 Message-ID: <539ED25A.4000009@suse.de> Date: Mon, 16 Jun 2014 13:17:46 +0200 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <539EC4B1.5090709@suse.de> <539ECDEA.1080606@suse.de> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [RFC v1 1/2] arm: Add the cortex-a9 CPU to the a9mpcore device List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Peter Crosthwaite , "qemu-devel@nongnu.org Developers" , Alistair Francis Am 16.06.2014 13:11, schrieb Peter Maydell: > On 16 June 2014 11:58, Andreas F=C3=A4rber wrote: >> Well, for Cortex-A9 that may work. But Cortex-A15 (and Cortex-A5x if >> existant by now) should also be refactored alongside, as proof of >> concept - can you really create num_cpu cortex-a15 CPUs on the MPCore >> for a big.LITTLE configuration? I'd be really surprised if there were >> separate MPCore devices per cluster. That would then indicate that the >> homogeneity assumption among CPUs within an MPCore is wrong and we nee= d >> to let its parent create the CPUs rather than an MPCore property. >=20 > Not sure what the relevance of big.LITTLE is here -- QEMU > simply doesn't support heterogenous CPU configurations so > we can't model big.LITTLE at all. Not today, but neither can the user fiddle with properties before realize today. So better not put blockers to known future features, in particular since I've been working into that direction. Two Cortex-As with identical software features and just different cache sizes like A53/A57 should be the easiest inhomogeneous configuration, compared to my Vybrid A5+M4 work. > If we did, it would be > via having a SoC with one a15mpcore and one a7mpcore. > (This is how the hardware does it -- there are two > multicore clusters, plus some cache coherency interconnect > magic.) Then I'm surprised and we have one issue less to worry about. :) Thanks, Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg