From: Sergey Fedorov <serge.fdrv@gmail.com>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
Fabian Aggeler <aggelerf@ethz.ch>
Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com,
qemu-devel@nongnu.org, christoffer.dall@linaro.org,
greg.bellows@linaro.org
Subject: Re: [Qemu-devel] [PATCH v3 07/32] target-arm: add non-secure Translation Block flag
Date: Tue, 17 Jun 2014 14:07:11 +0400 [thread overview]
Message-ID: <53A0134F.6040402@gmail.com> (raw)
In-Reply-To: <20140617091506.GH10398@toto>
On 17.06.2014 13:15, Edgar E. Iglesias wrote:
> Hi, I think the patch looks OK but I'm unsure if it brings any benefits
> unless we add separate TLBs for S and NS.
>
> I noticed that TTBR0 gets banked in the series, but are changes to
> SCR.NS flushing the TLBs? I might have missed that from the patches.
> You'll need it unless we add separate S/NS TLBs.
>
> Considering that changes to SCR.NS will flush the TLBs, the
> use of a per TB ns flag is limited, unless I am missing something...
Hi Edgar,
This seems to be used in patch 19/32.
// Sergey
>
> Cheers,
> Edgar
next prev parent reply other threads:[~2014-06-17 10:07 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-10 23:54 [Qemu-devel] [PATCH v3 00/32] target-arm: add Security Extensions for CPUs Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 01/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 02/32] target-arm: move Aarch32 SCR into security reglist Fabian Aggeler
2014-06-12 21:55 ` Greg Bellows
2014-06-17 7:22 ` Aggeler Fabian
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 03/32] target-arm: increase arrays of registers R13 & R14 Fabian Aggeler
2014-06-17 8:57 ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 04/32] target-arm: add arm_is_secure() function Fabian Aggeler
2014-06-11 12:17 ` Sergey Fedorov
2014-06-12 16:26 ` Greg Bellows
2014-06-12 17:26 ` Sergey Fedorov
2014-06-12 18:35 ` Greg Bellows
2014-06-12 19:09 ` Sergey Fedorov
2014-06-17 5:51 ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 05/32] target-arm: reject switching to monitor mode Fabian Aggeler
2014-06-12 21:55 ` Greg Bellows
2014-06-24 12:19 ` Aggeler Fabian
2014-06-24 13:43 ` Greg Bellows
2014-06-17 5:43 ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 06/32] target-arm: make arm_current_pl() return PL3 Fabian Aggeler
2014-06-17 5:40 ` Edgar E. Iglesias
2014-06-17 7:12 ` Aggeler Fabian
2014-06-17 7:07 ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 07/32] target-arm: add non-secure Translation Block flag Fabian Aggeler
2014-06-17 9:15 ` Edgar E. Iglesias
2014-06-17 10:07 ` Sergey Fedorov [this message]
2014-06-19 5:30 ` Edgar E. Iglesias
2014-06-25 4:15 ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 08/32] target-arm: A32: Emulate the SMC instruction Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 09/32] target-arm: extend Aarch32 async excp masking Fabian Aggeler
2014-06-17 7:48 ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 10/32] target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling Fabian Aggeler
2014-06-12 21:55 ` Greg Bellows
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 11/32] target-arm: add async excp target_el&mode function Fabian Aggeler
2014-06-12 21:56 ` Greg Bellows
2014-06-17 7:29 ` Aggeler Fabian
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 12/32] target-arm: use dedicated target_el function Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 13/32] target-arm: implement IRQ/FIQ routing to Monitor mode Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 14/32] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI Fabian Aggeler
2014-06-12 22:43 ` Greg Bellows
2014-06-17 7:36 ` Aggeler Fabian
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 15/32] target-arm: add NSACR register Fabian Aggeler
2014-06-13 18:27 ` Greg Bellows
2014-06-17 7:41 ` Aggeler Fabian
2014-06-24 15:37 ` Greg Bellows
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 16/32] target-arm: add SDER definition Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 17/32] target-arm: add MVBAR support Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 18/32] target-arm: add macros to access banked registers Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 19/32] target-arm: insert Aarch32 cpregs twice into hashtable Fabian Aggeler
2014-06-12 19:49 ` Sergey Fedorov
2014-06-25 5:20 ` Edgar E. Iglesias
2014-06-25 13:50 ` Greg Bellows
2014-06-26 3:56 ` Edgar E. Iglesias
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 20/32] target-arm: arrayfying fieldoffset for banking Fabian Aggeler
2014-06-13 20:18 ` Greg Bellows
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 21/32] target-arm: add SCTLR_EL3 and make SCTLR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 22/32] target-arm: make CSSELR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 23/32] target-arm: add TTBR0_EL3 and make TTBR0/1 banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 24/32] target-arm: add TCR_EL3 and make TTBCR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 25/32] target-arm: make c2_mask and c2_base_mask banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 26/32] target-arm: make DACR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 27/32] target-arm: make IFSR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 28/32] target-arm: make DFSR banked Fabian Aggeler
2014-06-13 22:06 ` Greg Bellows
2014-06-17 6:12 ` Edgar E. Iglesias
2014-06-23 16:53 ` Greg Bellows
2014-06-24 11:05 ` Aggeler Fabian
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 29/32] target-arm: make IFAR/DFAR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 30/32] target-arm: make PAR banked Fabian Aggeler
2014-06-13 22:49 ` Greg Bellows
2014-06-17 7:15 ` Aggeler Fabian
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 31/32] target-arm: make VBAR banked Fabian Aggeler
2014-06-13 22:43 ` Greg Bellows
2014-06-17 7:17 ` Aggeler Fabian
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 32/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) Fabian Aggeler
2014-06-23 21:40 ` Greg Bellows
2014-06-24 11:08 ` Aggeler Fabian
2014-06-11 1:31 ` [Qemu-devel] [PATCH v3 00/32] target-arm: add Security Extensions for CPUs Edgar E. Iglesias
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=53A0134F.6040402@gmail.com \
--to=serge.fdrv@gmail.com \
--cc=aggelerf@ethz.ch \
--cc=christoffer.dall@linaro.org \
--cc=edgar.iglesias@gmail.com \
--cc=greg.bellows@linaro.org \
--cc=peter.crosthwaite@xilinx.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).