Re: [Qemu-devel] [PATCH] target-ppc: fixed translation of mcrxr instruction

[Alexander Graf <agraf@suse.de>]

On 17.06.14 15:26, Tom Musta wrote:
> On 6/17/2014 12:54 AM, Sorav Bansal wrote:
>> Fixed bug in gen_mcrxr() in target-ppc/translate.c:
>> The XER[SO], XER[OV], and XER[CA] flags are stored in the least
>> significant bit (bit 0) of their respective registers. They need
>> to be shifted left (by their respective offsets) to generate the final
>> XER value. The old translation code for the 'mcrxr' instruction
>> was assuming that  the flags are stored in bit 2, and was shifting them
>> right (incorrectly)
>>
>> Signed-off-by: Sorav Bansal <sbansal@cse.iitd.ernet.in>
>> ---
>>   target-ppc/translate.c |    5 +++--
>>   1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
>> index 4801721..c5d73d5 100644
>> --- a/target-ppc/translate.c
>> +++ b/target-ppc/translate.c
>> @@ -4123,8 +4123,9 @@ static void gen_mcrxr(DisasContext *ctx)
>>       tcg_gen_trunc_tl_i32(t0, cpu_so);
>>       tcg_gen_trunc_tl_i32(t1, cpu_ov);
>>       tcg_gen_trunc_tl_i32(dst, cpu_ca);
>> -    tcg_gen_shri_i32(t0, t0, 2);
>> -    tcg_gen_shri_i32(t1, t1, 1);
>> +    tcg_gen_shli_i32(t0, t0, 3);
>> +    tcg_gen_shli_i32(t1, t1, 2);
>> +    tcg_gen_shli_i32(dst, dst, 1);
>>       tcg_gen_or_i32(dst, dst, t0);
>>       tcg_gen_or_i32(dst, dst, t1);
>>       tcg_temp_free_i32(t0);
>>
> Reviewed-by: Tom Musta <tommusta@gmail.com>
> Tested-by: Tom Musta <tommusta@gmail.com>

Thanks, applied to ppc-next.


Alex