From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46434) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WwtU7-0007ZC-E1 for qemu-devel@nongnu.org; Tue, 17 Jun 2014 09:31:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WwtTs-0004RA-20 for qemu-devel@nongnu.org; Tue, 17 Jun 2014 09:31:35 -0400 Message-ID: <53A04325.1020903@suse.de> Date: Tue, 17 Jun 2014 15:31:17 +0200 From: Alexander Graf MIME-Version: 1.0 References: <1402984442-13732-1-git-send-email-sbansal@cse.iitd.ernet.in> <53A04209.1040405@gmail.com> In-Reply-To: <53A04209.1040405@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-ppc: fixed translation of mcrxr instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tom Musta , Sorav Bansal , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org On 17.06.14 15:26, Tom Musta wrote: > On 6/17/2014 12:54 AM, Sorav Bansal wrote: >> Fixed bug in gen_mcrxr() in target-ppc/translate.c: >> The XER[SO], XER[OV], and XER[CA] flags are stored in the least >> significant bit (bit 0) of their respective registers. They need >> to be shifted left (by their respective offsets) to generate the final >> XER value. The old translation code for the 'mcrxr' instruction >> was assuming that the flags are stored in bit 2, and was shifting them >> right (incorrectly) >> >> Signed-off-by: Sorav Bansal >> --- >> target-ppc/translate.c | 5 +++-- >> 1 file changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/target-ppc/translate.c b/target-ppc/translate.c >> index 4801721..c5d73d5 100644 >> --- a/target-ppc/translate.c >> +++ b/target-ppc/translate.c >> @@ -4123,8 +4123,9 @@ static void gen_mcrxr(DisasContext *ctx) >> tcg_gen_trunc_tl_i32(t0, cpu_so); >> tcg_gen_trunc_tl_i32(t1, cpu_ov); >> tcg_gen_trunc_tl_i32(dst, cpu_ca); >> - tcg_gen_shri_i32(t0, t0, 2); >> - tcg_gen_shri_i32(t1, t1, 1); >> + tcg_gen_shli_i32(t0, t0, 3); >> + tcg_gen_shli_i32(t1, t1, 2); >> + tcg_gen_shli_i32(dst, dst, 1); >> tcg_gen_or_i32(dst, dst, t0); >> tcg_gen_or_i32(dst, dst, t1); >> tcg_temp_free_i32(t0); >> > Reviewed-by: Tom Musta > Tested-by: Tom Musta Thanks, applied to ppc-next. Alex