Re: [Qemu-devel] [PATCH v2 16/22] target-mips: add new Floating Point instructions

[Leon Alrae <leon.alrae@imgtec.com>]

On 20/06/2014 22:14, Aurelien Jarno wrote:
>> In R6 all Floating Point instructions are supposed to be IEEE-2008 compliant
>> i.e. FIR.HAS2008 always 1. However, QEMU softfloat for MIPS has not been
>> updated yet.
> 
> I don't think we can "update" softfloat. The existing version has to
> stay to correctly emulate the existing CPU, and unfortunately things like
> the sNaN bit is not even configurable at runtime, but fixed at compile time
> (in softfloat-specialize.h). How do you plan to handle that?

I'm aware of this. By "update" softfloat I meant making it configurable
at runtime for MIPS depending on FIR.HAS2008, FCSR.NAN2008 and
FCSR.ABS2008 flags, so legacy MIPS FPU will be still available for
existing CPUs.

>> +DEF_HELPER_1(float_class_s, i32, i32)
>> +DEF_HELPER_1(float_class_d, i64, i64)
>> +
>> +DEF_HELPER_2(float_rint_s, i32, env, i32)
>> +DEF_HELPER_2(float_rint_d, i64, env, i64)
>> +
>> +DEF_HELPER_4(float_maddf_s, i32, env, i32, i32, i32)
>> +DEF_HELPER_4(float_maddf_d, i64, env, i64, i64, i64)
>> +
>> +DEF_HELPER_4(float_msubf_s, i32, env, i32, i32, i32)
>> +DEF_HELPER_4(float_msubf_d, i64, env, i64, i64, i64)
>> +
> 
> Why not using FOP_PROTO here?
> 

I'll correct it.

Thanks,
Leon