From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40449) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzSkq-0005C3-8Q for qemu-devel@nongnu.org; Tue, 24 Jun 2014 11:35:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WzSkg-00080P-QN for qemu-devel@nongnu.org; Tue, 24 Jun 2014 11:35:28 -0400 Received: from smtp.codeaurora.org ([198.145.11.231]:56717) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzSkg-00080D-LZ for qemu-devel@nongnu.org; Tue, 24 Jun 2014 11:35:18 -0400 Message-ID: <53A99AB4.60804@codeaurora.org> Date: Tue, 24 Jun 2014 11:35:16 -0400 From: Christopher Covington MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v1 4/7] target-arm: Implement pmccntr_sync function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alistair Francis Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, qemu-devel@nongnu.org On 06/23/2014 09:12 PM, Alistair Francis wrote: > This is used to synchronise the PMCCNTR counter and swap its > state between enabled and disabled if required. It must always > be called twice, both before and after any logic that could > change the state of the PMCCNTR counter. > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 31aa09c..0984eda 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -1051,6 +1051,17 @@ static inline bool cp_access_ok(int current_pl, > } > > /** > + * pmccntr_sync > + * @cpu: ARMCPU > + * > + * Syncronises the counter in the PMCCNTR. This must always be called twice, > + * once before any action that might effect the timer and again afterwards. > + * The fucntion is used to swap the state of the register if required. Nit: function -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by the Linux Foundation.