From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46966) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzkFP-0006jY-Ln for qemu-devel@nongnu.org; Wed, 25 Jun 2014 06:16:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WzkFG-00050z-Lr for qemu-devel@nongnu.org; Wed, 25 Jun 2014 06:16:11 -0400 Received: from mga02.intel.com ([134.134.136.20]:13969) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzkFG-00050s-GS for qemu-devel@nongnu.org; Wed, 25 Jun 2014 06:16:02 -0400 Message-ID: <53AAA141.1060509@intel.com> Date: Wed, 25 Jun 2014 18:15:29 +0800 From: "Chen, Tiejun" MIME-Version: 1.0 References: <20140625083121.GC32652@redhat.com> <53AA8ACF.3070101@redhat.com> <20140625084835.GF32652@redhat.com> <53AA8E7D.809@intel.com> <20140625090925.GH32652@redhat.com> <53AA9480.1010005@intel.com> <53AA96DF.6070501@redhat.com> <53AA9B58.6050803@intel.com> <20140625095533.GE6357@redhat.com> <53AA9D79.3080003@redhat.com> <20140625100926.GH6357@redhat.com> In-Reply-To: <20140625100926.GH6357@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" , Paolo Bonzini Cc: peter.maydell@linaro.org, xen-devel@lists.xensource.com, stefano.stabellini@eu.citrix.com, allen.m.kay@intel.com, qemu-devel@nongnu.org, Kelly.Zytaruk@amd.com, anthony.perard@citrix.com, anthony@codemonkey.ws, yang.z.zhang@intel.com On 2014/6/25 18:09, Michael S. Tsirkin wrote: > On Wed, Jun 25, 2014 at 11:59:21AM +0200, Paolo Bonzini wrote: >> Il 25/06/2014 11:55, Michael S. Tsirkin ha scritto: >>>> You're saying we will reserve a free BAR to address those information to >>>> expose to guest, but which device does this free BAR belong to? The video >>>> device? Or PCH/MCH? >>> >>> If you just want to pass a couple of IDs, then don't, it's a waste. >>> But I still don't know what problem you are trying to solve, >>> looking at guest driver did not help. >> >> It's not just a couple of IDs, it's also random fields of the MCH >> configuration space. Grep drivers/gpu/drm/i915 for bridge_dev. >> >> Paolo > > I did, it seems to look for device at 0,0: > > static int i915_get_bridge_dev(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); > if (!dev_priv->bridge_dev) { > DRM_ERROR("bridge device not found\n"); > return -1; > } > return 0; > } > > are you sure this is the ISA bridge device? these patches put it at 1f. > :) The IGD is too complex to understand. The i915 driver needs to access that host bridge at 00:00.0, and this is addressed in patch #3. Also the i915 needs that ISA bridge at 00:1f.0, this is just what we're discussing now. Thanks Tiejun