From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43426) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X0AIi-0006PQ-9W for qemu-devel@nongnu.org; Thu, 26 Jun 2014 10:05:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X0AIa-0000fR-Qg for qemu-devel@nongnu.org; Thu, 26 Jun 2014 10:05:20 -0400 Received: from mx1.redhat.com ([209.132.183.28]:22950) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X0AIa-0000f3-I8 for qemu-devel@nongnu.org; Thu, 26 Jun 2014 10:05:12 -0400 Message-ID: <53AC2892.6030509@redhat.com> Date: Thu, 26 Jun 2014 16:05:06 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] About AddressSpace in intel-iommu emulation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Le Tan Cc: Jan Kiszka , qemu-devel Il 26/06/2014 16:01, Le Tan ha scritto: > Hi Paolo, > I am adding intel-iommu emulation to q35 for the GSoC project. I am > confused about AddressSpace and I believe that you can help me. :) > 1. For intel-iommu emulation, I have to read the translation > structures from guest memory, that is, the guest will prepare some > tables in memory and write the physical address of them to a register > of intel-iommu, and I need to access those structures. I use > dma_memory_read(&address_space_memory,...) to do this. Is that right? > I am not sure that whether accesses to address_space_memory will be > translated through IOMMU. I think the answer is not, because I see > that cpu_physical_memory_read() also use address_space_memory as > AddressSpace. Correct. > 2. In my opinion, I have to init a AddressSpace and link it with my > IOMMU MemoryRegion, then the bus uses this AddressSpace to translate > the accesses. Is that right? For q35, how can I register my IOMMU > MemoryRegion to the bus? I see that there is function > pci_setup_iommu() that links a AddressSpace to the bus to translate > accesses to PCI into system memory. Is that related? I think q35 > should maintain a bus AddressSpace, but I can't find it. > What do you think? Right now, the q35 PCI host does not define an iommu_fn, so the default DMA address space is used by pci_device_iommu_address_space. This is just address_space_memory. The iommu_fn is set with pci_setup_iommu. Commit ae74bbe (apb: implement IOMMU translation for PCI host bridge, 2014-05-28) provides an example of how to prepare an IOMMU memory region, add it to an address space, and return that address space from an iommu_fn. Thanks, Paolo > Thanks very much! > > Regards, > Le Tan >