From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57364) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X0TDA-0003RR-S9 for qemu-devel@nongnu.org; Fri, 27 Jun 2014 06:16:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X0TD6-0003Cx-7t for qemu-devel@nongnu.org; Fri, 27 Jun 2014 06:16:52 -0400 Received: from [59.151.112.132] (port=36223 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X0TD5-0003CF-2F for qemu-devel@nongnu.org; Fri, 27 Jun 2014 06:16:48 -0400 Message-ID: <53AD41DF.6000707@cn.fujitsu.com> Date: Fri, 27 Jun 2014 18:05:19 +0800 From: Gu Zheng MIME-Version: 1.0 References: <53AD4104.80701@cn.fujitsu.com> In-Reply-To: <53AD4104.80701@cn.fujitsu.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [RFC PATCH 3/3] cpu: add device_add foo-x86_64-cpu support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Eduardo Habkost , tangchen , Yasuaki Ishimatsu , ChenFan , Igor Mammedov , =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= From: Chen Fan Add support to device_add foo-x86_64-cpu, and additional checks of apic id are added into x86_cpuid_set_apic_id() and x86_cpu_apic_create() for duplicate. Besides, in order to support "device/device_add foo-x86_64-cpu" which without specified apic id, we add a new function get_free_apic_id() to provide the first free apid id each time to avoid apic id duplicate. Signed-off-by: Chen Fan Signed-off-by: Gu Zheng --- include/qom/cpu.h | 1 + qdev-monitor.c | 1 + target-i386/cpu.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++- target-i386/topology.h | 18 +++++++++++++ 4 files changed, 83 insertions(+), 1 deletions(-) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 87eecd2..87bd652 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -291,6 +291,7 @@ struct CPUState { QTAILQ_HEAD(CPUTailQ, CPUState); extern struct CPUTailQ cpus; #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node) +#define CPU_REMOVE(cpu) QTAILQ_REMOVE(&cpus, cpu, node) #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node) #define CPU_FOREACH_SAFE(cpu, next_cpu) \ QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu) diff --git a/qdev-monitor.c b/qdev-monitor.c index f87f3d8..48327c8 100644 --- a/qdev-monitor.c +++ b/qdev-monitor.c @@ -24,6 +24,7 @@ #include "qmp-commands.h" #include "sysemu/arch_init.h" #include "qemu/config-file.h" +#include "qom/object_interfaces.h" /* * Aliases were a bad idea from the start. Let's keep them diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 10f6d53..b058b70 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -49,6 +49,7 @@ #include "hw/i386/apic_internal.h" #endif +#include "qom/object_interfaces.h" /* Cache topology CPUID constants: */ @@ -1550,6 +1551,7 @@ static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque, const int64_t max = UINT32_MAX; Error *error = NULL; int64_t value; + X86CPUTopoInfo topo; if (dev->realized) { error_setg(errp, "Attempt to set property '%s' on '%s' after " @@ -1569,10 +1571,24 @@ static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque, return; } + if (value > x86_cpu_apic_id_from_index(max_cpus - 1)) { + error_setg(errp, "CPU with APIC ID %" PRIi64 + " is more than MAX APIC ID limits", value); + return; + } + + x86_topo_ids_from_apic_id(smp_cores, smp_threads, value, &topo); + if (topo.smt_id >= smp_threads || topo.core_id >= smp_cores) { + error_setg(errp, "CPU with APIC ID %" PRIi64 " does not match " + "topology configuration.", value); + return; + } + if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) { error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value); return; } + cpu->env.cpuid_apic_id = value; } @@ -1994,12 +2010,22 @@ out: return cpu; } +static void x86_cpu_cpudef_instance_init(Object *obj) +{ + DeviceState *dev = DEVICE(obj); + + dev->hotplugged = true; +} + static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) { X86CPUDefinition *cpudef = data; X86CPUClass *xcc = X86_CPU_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); xcc->cpu_def = cpudef; + + dc->cannot_instantiate_with_device_add_yet = false; } static void x86_register_cpudef_type(X86CPUDefinition *def) @@ -2008,6 +2034,8 @@ static void x86_register_cpudef_type(X86CPUDefinition *def) TypeInfo ti = { .name = typename, .parent = TYPE_X86_CPU, + .instance_size = sizeof(X86CPU), + .instance_init = x86_cpu_cpudef_instance_init, .class_init = x86_cpu_cpudef_class_init, .class_data = def, }; @@ -2544,8 +2572,17 @@ static void x86_cpu_apic_create(X86CPU *cpu, Error **errp) return; } + if (env->cpuid_apic_id > x86_cpu_apic_id_from_index(max_cpus - 1)) { + error_setg(errp, "CPU with APIC ID %" PRIi32 + " is more than MAX APIC ID:%" PRIi32, + env->cpuid_apic_id, + x86_cpu_apic_id_from_index(max_cpus - 1)); + return; + } + object_property_add_child(OBJECT(cpu), "apic", OBJECT(cpu->apic_state), NULL); + qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id); /* TODO: convert to link<> */ apic = APIC_COMMON(cpu->apic_state); @@ -2681,6 +2718,21 @@ uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) } } +static uint32_t get_free_apic_id(void) +{ + int i; + + for (i = 0; i < max_cpus; i++) { + uint32_t id = x86_cpu_apic_id_from_index(i); + + if (!cpu_exists(id)) { + return id; + } + } + + return x86_cpu_apic_id_from_index(max_cpus); +} + static void x86_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); @@ -2688,7 +2740,9 @@ static void x86_cpu_initfn(Object *obj) X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); CPUX86State *env = &cpu->env; static int inited; + uint32_t value; + value = get_free_apic_id(); cs->env_ptr = env; cpu_exec_init(env); @@ -2727,7 +2781,7 @@ static void x86_cpu_initfn(Object *obj) NULL, NULL, (void *)cpu->filtered_features, NULL); cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY; - env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index); + env->cpuid_apic_id = value; x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort); @@ -2741,6 +2795,13 @@ static void x86_cpu_initfn(Object *obj) } } +static void x86_cpu_finalizefn(Object *obj) +{ + CPUState *cs = CPU(obj); + + CPU_REMOVE(cs); +} + static int64_t x86_cpu_get_arch_id(CPUState *cs) { X86CPU *cpu = X86_CPU(cs); @@ -2841,6 +2902,7 @@ static const TypeInfo x86_cpu_type_info = { .parent = TYPE_CPU, .instance_size = sizeof(X86CPU), .instance_init = x86_cpu_initfn, + .instance_finalize = x86_cpu_finalizefn, .abstract = true, .class_size = sizeof(X86CPUClass), .class_init = x86_cpu_common_class_init, diff --git a/target-i386/topology.h b/target-i386/topology.h index e9ff89c..dcb4988 100644 --- a/target-i386/topology.h +++ b/target-i386/topology.h @@ -132,4 +132,22 @@ static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_cores, return apicid_from_topo_ids(nr_cores, nr_threads, &topo); } +/* Calculate CPU topology based on CPU APIC ID. + */ +static inline void x86_topo_ids_from_apic_id(unsigned nr_cores, + unsigned nr_threads, + apic_id_t apic_id, + X86CPUTopoInfo *topo) +{ + unsigned offset_mask; + topo->pkg_id = apic_id >> apicid_pkg_offset(nr_cores, nr_threads); + + offset_mask = (1L << apicid_pkg_offset(nr_cores, nr_threads)) - 1; + topo->core_id = (apic_id & offset_mask) + >> apicid_core_offset(nr_cores, nr_threads); + + offset_mask = (1L << apicid_core_offset(nr_cores, nr_threads)) - 1; + topo->smt_id = apic_id & offset_mask; +} + #endif /* TARGET_I386_TOPOLOGY_H */ -- 1.7.7