From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44352) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1Zbz-0006El-Ix for qemu-devel@nongnu.org; Mon, 30 Jun 2014 07:19:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1Zbp-0003GR-VS for qemu-devel@nongnu.org; Mon, 30 Jun 2014 07:19:03 -0400 Received: from mail-wi0-x231.google.com ([2a00:1450:400c:c05::231]:64189) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1Zbp-0003Fm-O2 for qemu-devel@nongnu.org; Mon, 30 Jun 2014 07:18:53 -0400 Received: by mail-wi0-f177.google.com with SMTP id r20so5805791wiv.10 for ; Mon, 30 Jun 2014 04:18:52 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <53B1479B.3030707@redhat.com> Date: Mon, 30 Jun 2014 13:18:51 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <53AA96DF.6070501@redhat.com> <53AA9B58.6050803@intel.com> <53AA9C4E.9070506@redhat.com> <53ABE551.3080407@intel.com> <53ABF00E.6000309@redhat.com> <53B0D0C5.60000@intel.com> <20140630064822.GB14491@redhat.com> <53B110CA.6070606@intel.com> <20140630090511.GB15777@redhat.com> <53B1300D.10001@intel.com> <20140630095509.GA17700@redhat.com> <53B139E6.1020607@intel.com> In-Reply-To: <53B139E6.1020607@intel.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Chen, Tiejun" , "Michael S. Tsirkin" Cc: peter.maydell@linaro.org, xen-devel@lists.xensource.com, stefano.stabellini@eu.citrix.com, allen.m.kay@intel.com, Kelly.Zytaruk@amd.com, qemu-devel@nongnu.org, yang.z.zhang@intel.com, anthony@codemonkey.ws, anthony.perard@citrix.com Il 30/06/2014 12:20, Chen, Tiejun ha scritto: > > I already post this to mainline to change as follows: > > - while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { > + pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0)); > + if (pch) { > > Please refer to this, > > [RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead > of check class type > > Linux Native guys would like to accept this. And actually Windows always > use devfn to detect this. Fair enough, but that means that, when using IGD, Q35 will have to move the ISA bridge off 1f.0. To me it seems fairly clear that as things stand IGD is not virtualizable without PV support. We're beating a dead horse. Paolo