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From: "Chen, Tiejun" <tiejun.chen@intel.com>
To: "Michael S. Tsirkin" <mst@redhat.com>
Cc: xen-devel@lists.xensource.com, airlied@linux.ie,
	daniel.vetter@ffwll.ch, intel-gfx@lists.freedesktop.org,
	linux-kernel@vger.kernel.org, jani.nikula@linux.intel.com,
	qemu-devel@nongnu.org, dri-devel@lists.freedesktop.org
Subject: Re: [Qemu-devel] [RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type
Date: Wed, 02 Jul 2014 16:27:57 +0800	[thread overview]
Message-ID: <53B3C28D.4020809@intel.com> (raw)
In-Reply-To: <20140702062104.GA3874@redhat.com>

On 2014/7/2 14:21, Michael S. Tsirkin wrote:
> On Thu, Jun 19, 2014 at 05:53:51PM +0800, Tiejun Chen wrote:
>> Originally the reason to probe ISA bridge instead of Dev31:Fun0
>> is to make graphics device passthrough work easy for VMM, that
>> only need to expose ISA bridge to let driver know the real
>> hardware underneath. This is a requirement from virtualization
>> team. Especially in that virtualized environments, XEN, there
>> is irrelevant ISA bridge in the system with that legacy qemu
>> version specific to xen, qemu-xen-traditional. So to work
>> reliably, we should scan through all the ISA bridge devices
>> and check for the first match, instead of only checking the
>> first one.
>>
>> But actually, qemu-xen-traditional, is always enumerated with
>> Dev31:Fun0, 00:1f.0 as follows:
>>
>> hw/pt-graphics.c:
>>
>> intel_pch_init()
>>      |
>>      + pci_isa_bridge_init(bus, PCI_DEVFN(0x1f, 0), ...);
>>
>> so this mean that isa bridge is still represented with Dev31:Func0
>> like the native OS. Furthermore, currently we're pushing VGA
>> passthrough support into qemu upstream, and with some discussion,
>> we wouldn't set the bridge class type and just expose this devfn.
>>
>> So we just go back to check devfn to make life normal.
>>
>> Signed-off-by: Tiejun Chen <tiejun.chen@intel.com>
>
> Making sure all relevant people are Cc'd.

Are you saying you and Paolo? Or others I'm missing?

>
> I think we should wait for the hypervisor to settle
> on what it wants to implement before making guest
> changes. Otherwise we'll just add more guest configurations
> that need to be supported.

Agreed. Actually this is why I just send this by RFC.

Thanks
Tiejun

>
>
>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.c | 19 +++----------------
>>   1 file changed, 3 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index 651e65e..cb2526e 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -417,18 +417,8 @@ void intel_detect_pch(struct drm_device *dev)
>>   		return;
>>   	}
>>
>> -	/*
>> -	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
>> -	 * make graphics device passthrough work easy for VMM, that only
>> -	 * need to expose ISA bridge to let driver know the real hardware
>> -	 * underneath. This is a requirement from virtualization team.
>> -	 *
>> -	 * In some virtualized environments (e.g. XEN), there is irrelevant
>> -	 * ISA bridge in the system. To work reliably, we should scan trhough
>> -	 * all the ISA bridge devices and check for the first match, instead
>> -	 * of only checking the first one.
>> -	 */
>> -	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
>> +	pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
>> +	if (pch) {
>>   		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
>>   			unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
>>   			dev_priv->pch_id = id;
>> @@ -462,10 +452,7 @@ void intel_detect_pch(struct drm_device *dev)
>>   				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
>>   				WARN_ON(!IS_HASWELL(dev));
>>   				WARN_ON(!IS_ULT(dev));
>> -			} else
>> -				continue;
>> -
>> -			break;
>> +			}
>>   		}
>>   	}
>>   	if (!pch)
>> --
>> 1.9.1
>>
>
>

      reply	other threads:[~2014-07-02  8:28 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-19  9:53 [Qemu-devel] [RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type Tiejun Chen
2014-06-20  9:40 ` Chen, Tiejun
2014-06-20 12:32   ` Daniel Vetter
2014-06-22  8:00     ` Chen, Tiejun
2014-06-20 12:48 ` Paolo Bonzini
2014-06-22  8:25   ` Chen, Tiejun
2014-06-25  6:48     ` Paolo Bonzini
2014-06-25  7:34       ` Chen, Tiejun
2014-06-25  7:55         ` Paolo Bonzini
2014-06-30  3:13           ` Chen, Tiejun
2014-06-30 10:56             ` Paolo Bonzini
2014-07-07 14:49       ` Daniel Vetter
2014-07-07 14:57         ` Paolo Bonzini
2014-07-07 17:54           ` [Qemu-devel] [Intel-gfx] " Daniel Vetter
2014-07-07 17:58             ` Paolo Bonzini
2014-07-07 18:40               ` Daniel Vetter
2014-07-10 21:08                 ` Tian, Kevin
2014-07-11  6:29                   ` Daniel Vetter
2014-07-11 19:42                     ` [Qemu-devel] [Xen-devel] " Konrad Rzeszutek Wilk
2014-07-11 20:30                       ` Tian, Kevin
2014-07-12 10:13                         ` [Qemu-devel] [Intel-gfx] [Xen-devel] " Daniel Vetter
2014-06-24  2:59 ` [Qemu-devel] [Intel-gfx] " Zhenyu Wang
2014-06-25  2:28   ` Chen, Tiejun
2014-07-07 14:51     ` Daniel Vetter
2014-06-30 11:18 ` [Qemu-devel] " Michael S. Tsirkin
2014-07-01  1:52   ` Chen, Tiejun
2014-07-02  6:21 ` Michael S. Tsirkin
2014-07-02  8:27   ` Chen, Tiejun [this message]

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