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Subject: Re: [Qemu-devel] [RFC] alpha qemu arithmetic exceptions
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To: Al Viro <viro@ZenIV.linux.org.uk>
Cc: Peter Maydell <peter.maydell@linaro.org>, QEMU Developers <qemu-devel@nongnu.org>

On 07/03/2014 11:25 AM, Al Viro wrote:
> On Thu, Jul 03, 2014 at 07:51:04AM +0100, Al Viro wrote:
> 
>> FWIW, why not just generate
>> 	trunc_i64_i32 tmp, va
>> 	trunc_i64_i32 tmp2, vb
>> 	muls2_i32 tmp2, tmp, tmp, tmp2
>> 	ext32s_i64 vc, tmp2
>> 	maybe_overflow_32 tmp
>> where maybe_overflow throws IOV unless tmp is 0 or -1?
>> to suffice for mull/v.  mulq/v would be
>> 	muls2_i64 vc, tmp, va, vb
>> 	maybe_overflow_64 tmp
>> addl/v:
>> 	trunc_i64_i32 tmp, va
>> 	trunc_i64_i32 tmp2, vb
>> 	add2_i32 tmp2, tmp, tmp, zero, tmp2, zero
>> 	ext32s_i64 vc, tmp2
>> 	maybe_overflow_32 tmp
>> etc.
> 
> Grr...  Wrong check, obviously - we want to check that tmp + MSB(tmp2) is 0.
> Something like
> 	setcond_32	tmp2, tmp2, zero, TCG_COND_LT
> 	add_i32		tmp, tmp2, tmp
> 	call		helper_IOV_if_not_zero tmp
> for 32bit ones and
> 	setcond_64	tmp2, vc, zero, TCG_COND_LT
> 	add_i64		tmp, tmp2, tmp
> 	call		helper_IOV_if_not_zero tmp
> for 64bit ones, or would it be better just to pass both arguments to helper
> and let it deal with the check?  I'm not familiar enough with TCG, sorry...
> 

I believe I have a tidy solution to these /v insns.  New patch set shortly.


r~