From: Richard Henderson <rth@twiddle.net>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: Re: [Qemu-devel] [PATCH 09/15] target-tricore: Add instructions of SRRS and SLRO opcode format.
Date: Mon, 07 Jul 2014 13:30:20 -0700 [thread overview]
Message-ID: <53BB035C.3000501@twiddle.net> (raw)
In-Reply-To: <1404756822-3253-10-git-send-email-kbastian@mail.uni-paderborn.de>
On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> +/* Functions for load/save to/from memory */
> +#define OP_MEM_INDIRECT(insn) \
> +static inline void gen_indirect_##insn(DisasContext *ctx, TCGv r1, TCGv r2, \
> + int16_t con) \
> +{ \
> + TCGv temp = tcg_temp_new(); \
> + TCGv tempPC = tcg_const_i32(ctx->pc); \
> + tcg_gen_addi_tl(temp, r2, con); \
> + tcg_gen_qemu_##insn(r1, temp, ctx->mem_idx); \
> + tcg_temp_free(tempPC); \
> + tcg_temp_free(temp); \
> +}
> +OP_MEM_INDIRECT(ld8s)
> +OP_MEM_INDIRECT(ld8u)
> +OP_MEM_INDIRECT(ld16s)
> +OP_MEM_INDIRECT(ld16u)
> +OP_MEM_INDIRECT(ld32s)
> +OP_MEM_INDIRECT(ld32u)
Please just rearrange all of your memory operations to use the new TCGMemOp
enumeration and the common tcg_gen_qemu_{ld,st}_tl functions.
I nearly suggested that for patch 8, but it's quite obvious here.
tempPC is unused here.
Why call this "indirect"? A better term would be "offset".
r~
next prev parent reply other threads:[~2014-07-07 20:30 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
2014-07-07 18:13 ` [Qemu-devel] [PATCH 01/15] target-tricore: Add target stubs and qom-cpu Bastian Koppelmann
2014-07-07 19:09 ` Richard Henderson
2014-07-07 19:14 ` Richard Henderson
2014-07-07 19:24 ` Peter Maydell
2014-07-11 11:05 ` Bastian Koppelmann
2014-07-11 11:10 ` Peter Maydell
2014-07-07 18:13 ` [Qemu-devel] [PATCH 02/15] target-tricore: Add board for systemmode Bastian Koppelmann
2014-07-07 18:13 ` [Qemu-devel] [PATCH 03/15] target-tricore: Add softmmu support Bastian Koppelmann
2014-07-07 18:13 ` [Qemu-devel] [PATCH 04/15] target-tricore: Add initialization for translation Bastian Koppelmann
2014-07-07 18:13 ` [Qemu-devel] [PATCH 05/15] target-tricore: Add masks and opcodes for decoding Bastian Koppelmann
2014-07-07 19:37 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 06/15] target-tricore: Add instructions of SRC opcode format Bastian Koppelmann
2014-07-07 20:06 ` Richard Henderson
2014-07-07 20:56 ` Max Filippov
2014-07-07 18:13 ` [Qemu-devel] [PATCH 07/15] target-tricore: Add instructions of SRR " Bastian Koppelmann
2014-07-07 20:17 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 08/15] target-tricore: Add instructions of SSR " Bastian Koppelmann
2014-07-07 20:22 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 09/15] target-tricore: Add instructions of SRRS and SLRO " Bastian Koppelmann
2014-07-07 20:30 ` Richard Henderson [this message]
2014-07-07 18:13 ` [Qemu-devel] [PATCH 10/15] target-tricore: Add instructions of SB " Bastian Koppelmann
2014-07-08 4:41 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 11/15] target-tricore: Add instructions of SBC and SBRN " Bastian Koppelmann
2014-07-08 4:47 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 12/15] target-tricore: Add instructions of SBR " Bastian Koppelmann
2014-07-08 5:26 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 13/15] target-tricore: Add instructions of SC " Bastian Koppelmann
2014-07-08 5:32 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 14/15] target-tricore: Add instructions of SLR, SSRO and SRO " Bastian Koppelmann
2014-07-08 5:36 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 15/15] target-tricore: Add instructions of SR " Bastian Koppelmann
2014-07-08 5:58 ` Richard Henderson
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