From: Leon Alrae <leon.alrae@imgtec.com>
To: Aurelien Jarno <aurelien@aurel32.net>
Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 08/12] target-mips: add BadInstr and BadInstrP support
Date: Tue, 8 Jul 2014 09:07:50 +0100 [thread overview]
Message-ID: <53BBA6D6.8080507@imgtec.com> (raw)
In-Reply-To: <20140619221347.GA22451@ohm.rr44.fr>
On 19/06/2014 23:13, Aurelien Jarno wrote:
> I don't think this should implemented that way, as it would have a
> significant impact on the performances. Given we have the fault address
> (we fill EPC), we can fetch the corresponding opcode. There might be
> some code change to do for the branches, so that we can get the
> informations we need from re-translation (this might also simplify the
> current branches code).
I changed the BadInstr implementation in v2. Now the instruction word is
fetched when we have the exception (and the valid instruction word is
available), so we don't have to generate code to save the last
instruction. The same has been done for BadInstrP and the branch prior
to the delay slot.
Thanks,
Leon
next prev parent reply other threads:[~2014-07-08 8:08 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-19 14:45 [Qemu-devel] [PATCH 00/12] implement features required in MIPS64 Release 6 Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 01/12] target-mips: add KScratch registers Leon Alrae
2014-06-20 22:02 ` Aurelien Jarno
2014-07-08 8:18 ` Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 02/12] target-mips: update cpu_save/cpu_load to support " Leon Alrae
2014-06-19 17:43 ` Richard Henderson
2014-07-08 8:31 ` Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 03/12] target-mips: distinguish between data load and instruction fetch Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 04/12] target-mips: add RI and XI fields to TLB entry Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 05/12] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1} Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 06/12] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 07/12] target-mips: add TLBINV support Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 08/12] target-mips: add BadInstr and BadInstrP support Leon Alrae
2014-06-19 22:13 ` Aurelien Jarno
2014-07-08 8:07 ` Leon Alrae [this message]
2014-06-19 14:45 ` [Qemu-devel] [PATCH 09/12] target-mips: save cpu state if instruction can cause an exception Leon Alrae
2014-06-19 22:13 ` Aurelien Jarno
2014-06-19 14:45 ` [Qemu-devel] [PATCH 10/12] target-mips: update cpu_save/cpu_load to support BadInstr registers Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 11/12] target-mips: enable features in MIPS32R5-generic core Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 12/12] target-mips: enable features in MIPS64R6-generic core Leon Alrae
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