From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36478) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X71eO-0002ps-Q0 for qemu-devel@nongnu.org; Tue, 15 Jul 2014 08:16:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X71eH-0000k8-5A for qemu-devel@nongnu.org; Tue, 15 Jul 2014 08:16:04 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:26608) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X71eG-0000je-Rd for qemu-devel@nongnu.org; Tue, 15 Jul 2014 08:15:57 -0400 Message-ID: <53C52A5A.9090005@mail.uni-paderborn.de> Date: Tue, 15 Jul 2014 14:19:22 +0100 From: Bastian Koppelmann MIME-Version: 1.0 References: <1405359671-25985-1-git-send-email-kbastian@mail.uni-paderborn.de> <1405359671-25985-7-git-send-email-kbastian@mail.uni-paderborn.de> <53C4461F.2070005@twiddle.net> In-Reply-To: <53C4461F.2070005@twiddle.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 06/15] target-tricore: Add instructions of SRC opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org >> + tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); > Are you planning to come back to implement V and AV bits later? Would you recommend implementing this as a helper? It seems rather complex. Especially with half-word and byte arithmetic. On the other hand the instructions using this are common and would benefit from open-coding it in TCG. Thanks, Bastian